eCPRI Intel® FPGA IP Design Example User Guide

Download PDF
ID 683837
Date 8/16/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. eCPRI Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for the eCPRI Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling the Compilation-Only Project 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the eCPRI Intel FPGA IP Design Example 1.8. Generating and Downloading the Executable and Linking Format (.elf) Programming File
1.4. Simulating the Design Example Testbench x
1.4.1. Enabling Dynamic Reconfiguration to the Ethernet IP
2. Design Example Description x
2.1. Features 2.2. eCPRI IP Hardware Design Example 2.3. Simulation Design Example 2.4. eCPRI IP Design Example Interface Signals 2.5. Design Example Register Map
1. Quick Start Guide
2. Design Example Description
3. eCPRI Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for the eCPRI Intel® FPGA IP Design Example User Guide

1.2. Generating the Design

Prerequisite: Once you receive the eCPRI web-core IP, save the web-core installer to the local area. Run the installer with Windows/Linux. When prompted, install the web-core to the same location as Intel Quartus Prime folder. The eCPRI Intel FPGA IP now appears in the IP Catalog.

If you do not already have an Quartus® Prime Pro Edition project in which to integrate your eCPRI Intel® FPGA IP core, you must create one.

  1. In the Quartus® Prime Pro Edition software, click File > New Project Wizard to create a new Quartus® Prime project, or click File > Open Project to open an existing Quartus® Prime project. The wizard prompts you to specify a device.
  2. Specify the device family and a device that meets the speed grade requirements.
  3. Click Finish.
  4. In the IP Catalog, locate and double-click eCPRI Intel FPGA IP. The New IP Variant window appears.
Follow these steps to generate the eCPRI IP hardware design example and testbench:
  1. In the IP Catalog, locate and double-click eCPRI Intel FPGA IP. The New IP Variant window appears.
  2. Click OK. The parameter editor appears.
    Figure 2. Example Design Tab in the eCPRI Intel FPGA IP Parameter Editor
  3. Specify a top-level name <your_ip> for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip.
  4. Click OK. The parameter editor appears.
  5. On the General tab, specify the parameters for your IP core variation.
    Note:
    • You must turn on Streaming parameter in the eCPRI IP parameter editor when you generate the design example with Interworking Function (IWF) Support parameter enabled,
    • You must set the CPRI Line Bit Rate (Gbit/s) to Others when generating the design example with Interworking Function (IWF) Support parameter enabled.
  6. On the Example Design tab, select the simulation option to generate the testbench, select the synthesis option to generate the hardware example design, and select synthesis and simulation option to generate both the testbench and the hardware design example.
  7. For Language for top level simulation file, select Verilog or VHDL.
    Note: This option is available only when you select Simulation option for your example design.
  8. For Language for top level synthesis file, select Verilog or VHDL.
    Note: This option is available only when you select Synthesis option for your example design.
  9. For Number of Channels, you can enter the number of channels (1 to 4) intended for your design. Default value is 1.
  10. Click Generate Example Design. The Select Example Design Directory window appears.
  11. If you want to modify the design example directory path or name from the defaults displayed (ecpri_0_testbench), browse to the new path and type the new design example directory name.
  12. Click OK.
Related Information
Level Two Title