eCPRI Intel® FPGA IP Design Example User Guide

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ID 683837
Date 8/16/2024
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. eCPRI Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for the eCPRI Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling the Compilation-Only Project 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the eCPRI Intel FPGA IP Design Example 1.8. Generating and Downloading the Executable and Linking Format (.elf) Programming File
1.4. Simulating the Design Example Testbench x
1.4.1. Enabling Dynamic Reconfiguration to the Ethernet IP
2. Design Example Description x
2.1. Features 2.2. eCPRI IP Hardware Design Example 2.3. Simulation Design Example 2.4. eCPRI IP Design Example Interface Signals 2.5. Design Example Register Map
1. Quick Start Guide
2. Design Example Description
3. eCPRI Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for the eCPRI Intel® FPGA IP Design Example User Guide

1.3. Directory Structure

The eCPRI IP core design example file directories contain the following generated files for the design example.
Figure 3. Directory Structure of the Generated Example Design
Table 1.   eCPRI Intel® FPGA IP Core Testbench File Descriptions

File Names

Description

Key Testbench and Simulation Files

<design_example_dir>/simulation/testbench/ecpri_tb.sv Top-level testbench file. The testbench instantiates the DUT wrapper and runs Verilog HDL tasks to generate and accept packets.
<design_example_dir>/simulation/testbench/ecpri_ed.sv DUT wrapper that instantiates DUT and other testbench components.
<design_example_dir>/simulation/ed_fw/flow.c C-code source file.

Testbench Scripts

<design_example_dir>/simulation/setup_scripts/mentor/run_vsim.do The Siemens* EDA QuestaSim* script to run the testbench.
<design_example_dir>/simulation/setup_scripts/synopsys/vcs/run_vcs.sh The Synopsys* VCS* script to run the testbench.
<design_example_dir>/simulation/setup_scripts/synopsys/vcsmx/run_vcsmx.sh The Synopsys* VCS* MX script (combined Verilog HDL and SystemVerilog with VHDL) to run the testbench.
<design_example_dir>/simulation/setup_scripts/aldec/run_rivierapro.tcl The Aldec* Riviera-PRO* script to run the testbench.
<design_example_dir>/simulation/setup_scripts/xcelium/run_xcelium.sh The Cadence* Xcelium* script to run the testbench.
Table 2.   eCPRI Intel® FPGA IP Core Hardware Design Example File Descriptions
File Names Descriptions
<design_example_dir>/synthesis/quartus/ecpri_ed.qpf Quartus® Prime project file.
<design_example_dir>/synthesis/quartus/ecpri_ed.qsf Quartus® Prime project setting file.
<design_example_dir>/synthesis/quartus/ecpri_ed.sdc Synopsys Design Constraints files. You can copy and modify these files for your own Stratix® 10 design.
<design_example_dir>/synthesis/testbench/ecpri_ed_top.sv Top-level Verilog HDL design example file.
<design_example_dir>/synthesis/testbench/ecpri_ed.sv DUT wrapper that instantiates DUT and other testbench components.
<design_example_dir>/synthesis/quartus/ecpri_s10.tcl Main file for accessing System Console (Available in Stratix® 10 H-tile and E-tile designs).
<design_example_dir>/synthesis/quartus/ecpri_a10.tcl Main file for accessing System Console (Available in Arria® 10 designs).
<design_example_dir>/synthesis/quartus/ecpri_agilex.tcl Main file for accessing System Console (Available in Agilex™ 7 designs).
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