2.2. eCPRI IP Hardware Design Example
This topic describes the hardware design example components.
Figure 4. Block Diagram for Agilex™ 5 Designs
Figure 5. Block Diagram for Agilex™ 7 F-tile Designs
Figure 6. Block Diagram for Agilex™ 7 E-tile Designs
Figure 7. Block Diagram for Stratix® 10 Designs
Figure 8. Block Diagram for Arria® 10 Designs
eCPRI Intel® FPGA IP
Accepts data from the traffic generators instantiated within the test wrapper and prioritize the data for transmission to the Ethernet IP.
Ethernet IP
- F-tile Ethernet Intel FPGA Hard IP ( Agilex™ 7 F-tile designs)
- E-tile Hard IP for Ethernet ( Stratix® 10 or Agilex™ 7 E-tile designs)
- 25G Ethernet Stratix® 10 IP ( Stratix® 10 H-tile designs)
- Low Latency Ethernet 10G MAC IP and 1G/10GbE and 10GBASE-KR PHY IP ( Arria® 10 designs)
Precision Time Protocol (PTP) IO PLL
For Agilex 5 devices, the PTP IOPLL generates the PTP measurement sampling clock (126.984127 MHz) and TOD subsystem sampling clock (114.285714 MHz).
For Stratix® 10 H-tile designs—Instantiated to generate the latency measurement input reference clock for the Ethernet IP and sampling clock for Time of Day (TOD) subsystem. For 25G Ethernet Intel Stratix 10 FPGA IP with the IEEE 1588v2 feature, Intel® recommends you to set the frequency of this clock to 156.25 MHz. Refer to the 25G Ethernet Intel Stratix 10 FPGA IP User Guide and Intel Stratix 10 H-tile Transceiver PHY User Guide for more information. The PTP IOPLL also generates the reference clock for the eCPRI IO PLL in the cascading manner.
For Arria® 10 designs—Instantiated to generate the 312.5 MHz and 156.25 MHz clock inputs for the Low Latency Ethernet 10G MAC IP and 1G/10GbE, 10GBASE-KR PHY IP, and eCPRI IP.
eCPRI IO PLL
Generates IP clock output of 390.625 MHz for the TX and RX path of the eCPRI IP, and traffic components.
Note: This block is only in the design example generated for Agilex™ 5, Stratix® 10 and Agilex™ 7 devices.
IWF Type 0
Converts CPRI MAC data packet into eCPRI packet. This block sits between the CPRI MAC and eCPRI IP as shown in block diagram above. The conversion works only for message type 0,2, 6, and 7.
Note: The current version of the eCPRI Intel FPGA IP only supports IWF type 0. For Agilex™ 5 and Agilex™ 7 F-tile devices, the design example does not support IWF.
When you generate the design example with Interworking Function (IWF) Support off, the packet traffic flows directly from the test wrapper module to the Avalon streaming source and sink interface and external source and sink interface of the eCPRI IP.
When you generate the design example with Interworking Function (IWF) Support on, the packet traffic flows to the IWF Avalon streaming sink interface from the test wrapper module first, and coming out from IWF Avalon streaming source interface to the eCPRI Avalon streaming source andsink interface.
CPRI MAC
Provides the CPRI part of the layer 1 and full layer 2 protocols for the transfer of user plane, C&M, and synchronization information between REC and RE and between two RE,
CPRI PHY
Provides the remaining part of CPRI layer 1 protocol for line coding, bit error correction/detection, and etc.
Note: The CPRI MAC and CPRI PHY IP instantiated in this design example are configured to be running at single CPRI line rate 9.8 Gbps only. The design example does not support line rate autonegotiation in the current release.
Test Wrapper
Consists of traffic generators and checkers that generate different sets of data packets to the Avalon Streaming interfaces of the eCPRI IP as below:
- eCPRI packets to the Avalon-ST source/sink interfaces (IWF feature disabled):
- Only supports message type 2.
- Back-to-back mode generation with incremental pattern mode generation and payload size of 72 bytes for each packet.
- Configurable via CSR to run in either non-continuous or continuous mode.
- TX/RX packet statistic status available to access via CSR.
- eCPRI packets to the Avalon streaming source and sink interfaces (IWF feature enabled):
- Only supports message type 0 in current release.
- Incremental pattern mode generation with interpacket gap generation and payload size of 240 bytes for each packet.
- Configurable via CSR to run in either non-continuous or continuous mode.
- TX/RX packet statistic status available to access via CSR.
- Precision Time Protocol (1588 PTP) packet and non-PTP miscellaneous packets to the External source/sink interfaces:
- Static Ethernet header generation with pre-defined parameters: Ethertype- 0x88F7, Message type- Opcode 0 (Sync), and PTP version-0.
- Pre-defined pattern mode generation with interpacket gap of 2 cycles and payload size of 57 bytes for each packet.
- 128 packets are generated in the period of every one second.
- Configurable via CSR to run in either non-continuous or continuous mode.
- TX/RX packet statistic status available to access via CSR.
- External non-PTP miscellaneous packets:
- Static Ethernet Header generation with pre-defined parameter, Ethertype- 0x8100 (non-PTP).
- PRBS pattern mode generation with interpacket gap of 2 cycles and payload size of 128 bytes for each packet.
- Configurable via CSR to run in either non-continuous or continuous mode.
- TX/RX packet statistic status available to access via CSR.
Time of Day (TOD) subsystem
Contains two IEEE 1588 TOD modules for both TX and RX, and one IEEE 1588 TOD Synchronizer module generated by Quartus® Prime software.
Nios® V Subsystem
Consists of Avalon memory-mapped bridge that allows Avalon memory-mapped data arbitration between Nios® V processor, test wrapper, and Avalon® memory-mapped address decoder blocks.
Nios® V is responsible to perform data rate switching based on the output from test wrapper's rate_switch register value. This block programs the necessary register once it receives command from the test wrapper.
Note: This block is not present in the design example generated for Arria® 10 and Agilex™ 7 F-tile devices.
System Console
Provides an interface for you to do first-level debugging and monitor status of the IP, and the traffic generators and checkers.