1. Quick Start Guide
| Updated for: |
|---|
| Intel® Quartus® Prime Design Suite 24.1 |
| IP Version 3.0.2 |
The enhanced Common Public Radio Interface (eCPRI) Intel® FPGA IP core implements the eCPRI specification version 2.0. The eCPRI Intel® FPGA IP provides a simulation testbench and a hardware design example that supports compilation and hardware testing. When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design example in hardware.
The compiled hardware design example runs on:
- Intel® Agilex™ 7 I-Series FPGA Development Kit
- Intel® Agilex™ 7 I-Series Transceiver-SoC Development Kit
- Intel® Agilex™ 7 F-Series Transceiver-SoC Development Kit
- Stratix® 10 GX Transceiver Signal Integrity Development Kit for the H-tile design examples
- Stratix® 10 TX Transceiver Signal Integrity Development Kit for the E-tile design examples
- Arria® 10 GX Transceiver Signal Integrity Development Kit
The testbench and design example supports 25G and 10G data rates for Stratix® 10 H-tile or E-tile and Intel® Agilex™ 7 E-tile or F-tile device variations of the eCPRI IP.
Note: The eCPRI IP design example with interworking function (IWF) is only available for 9.8 Gbps CPRI line bit rate in the current release.
Note: The eCPRI IP design example does not support dynamic reconfiguration for 10G data rate in Arria® 10 designs.
The eCPRI Intel® FPGA IP core design example supports the following features:
- Internal TX to RX serial loopback mode
- Traffic generator and checker
- Basic packet checking capabilities
- Ability to use System Console to run the design and reset the design for re-testing purpose
Figure 1. Development Steps for the Design Example