eCPRI Intel® FPGA IP Design Example User Guide

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ID 683837
Date 5/18/2024
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. eCPRI Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for eCPRI Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling the Compilation-Only Project 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the eCPRI Intel FPGA IP Design Example 1.8. Generating and Downloading the Executable and Linking Format (.elf) Programming File
1.4. Simulating the Design Example Testbench x
1.4.1. Enabling Dynamic Reconfiguration to the Ethernet IP
2. Design Example Description x
2.1. Features 2.2. eCPRI IP Hardware Design Example 2.3. Simulation Design Example 2.4. Interface Signals 2.5. Design Example Register Map
1. Quick Start Guide
2. Design Example Description
3. eCPRI Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for eCPRI Intel® FPGA IP Design Example User Guide

2.4. Interface Signals

Table 5.  Design Example Interface Signals
Signal Direction Description
clk_ref Input Reference clock for the Ethernet MAC.
  • For Stratix® 10 E-tile, Intel® Agilex™ 7 E-tile and F-tile designs, 156.25 MHz clock input for the E-tile Ethernet Hard IP core or F-tile Ethernet Hard IP core. Connect to i_clk_ref[0] in the Ethernet Hard IP.
  • For Stratix® 10 H-tile designs, a 322.2625 MHz clock input for the Transceiver ATX PLL and 25G Ethernet IP. Connect to pll_refclk0[0] in the Transceiver ATX PLL and clk_ref[0] in 25G Ethernet IP.
  • For Arria® 10 designs, a 322.265625 MHz clock input for the Transceiver ATX PLL and 1G/10GbE and 10GBase-KR PHY IP. Connect to pll_refclk0[0] in the Transceiver ATX PLL and rx_cdr_ref_clk_10g[0] in the 1G/10GbE and 10G BASE-KR PHY IP.
tod_sync_sampling_clk Input For Intel Arria 10 designs, a 250 MHz clock input for TOD subsystem.
clk100 Input Management clock. This clock is used to generate latency_clk for PTP.

Drive at 100 MHz.
mgmt_reset_n Input Reset signal for Nios® V system.
tx_serial Output TX serial data. Supports up to 4 channels.
rx_serial Input RX serial data. Supports up to 4 channels.
iwf_cpri_ehip_ref_clk Input E-tile CPRI PHY reference clock input. This clock is only present in Stratix® 10 E-tile and Intel® Agilex™ 7 E-tile designs.

Drive at 153.6 MHz for 9.8 Gbps CPRI line rate.

iwf_cpri_pll_refclk0 Output CPRI TX PLL reference clock.
  • For Stratix® 10 H-tile designs: Drive at 307.2 MHz for CPRI data rate 9.8 Gbps.
  • For Stratix® 10 E-tile and Intel® Agilex™ 7 E-tile designs: Drive at 156.25 MHz for CPRI data rate 9.8 Gbps.
iwf_cpri_xcvr_cdr_refclk Output CPRI receiver CDR reference clock. This clock is only present in Stratix® 10 H-tile designs.

Drive at 307.2 MHz for 9.8 Gbps CPRI line rate.

iwf_cpri_xcvr_txdataout Output CPRI transmit serial data. Supports up to 4 channels.
iwf_cpri_xcvr_rxdatain Output CPRI receiver serial data. Supports up to 4 channels.
cpri_gmii_clk Input CPRI GMII 125 MHz input clock.
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