eCPRI Intel® FPGA IP Design Example User Guide

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ID 683837
Date 5/18/2024
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. eCPRI Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for eCPRI Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling the Compilation-Only Project 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the eCPRI Intel FPGA IP Design Example 1.8. Generating and Downloading the Executable and Linking Format (.elf) Programming File
1.4. Simulating the Design Example Testbench x
1.4.1. Enabling Dynamic Reconfiguration to the Ethernet IP
2. Design Example Description x
2.1. Features 2.2. eCPRI IP Hardware Design Example 2.3. Simulation Design Example 2.4. Interface Signals 2.5. Design Example Register Map
1. Quick Start Guide
2. Design Example Description
3. eCPRI Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for eCPRI Intel® FPGA IP Design Example User Guide

1.1. Hardware and Software Requirements

To test the example design, use the following hardware and software:
  • Quartus® Prime Pro Edition software version 24.1
  • System Console
  • Supported Simulators:
    • Siemens* EDA QuestaSim*
    • Synopsys* VCS*
    • Synopsys* VCS* MX
    • Aldec* Riviera-PRO*
    • Cadence* Xcelium*
  • Development Kit:
    • Intel® Agilex™ 7 I-Series FPGA Development Kit
    • Intel® Agilex™ 7 I-Series Transceiver-SoC Development Kit
    • Intel® Agilex™ 7 F-Series Transceiver-SoC Development Kit
    • Stratix® 10 GX Transceiver Signal Integrity Development Kit for the H-tile device variation design example
    • Stratix® 10 TX Transceiver Signal Integrity Development for the E-tile device variation design example
    • Arria® 10 GX Transceiver Signal Integrity Development Kit
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