Visible to Intel only — GUID: mwh1410384674209
Ixiasoft
Visible to Intel only — GUID: mwh1410384674209
Ixiasoft
3.4.6.10. Sequential Triggering
When the last triggering condition evaluates to TRUE, the Signal Tap logic analyzer starts the data acquisition. For segmented buffers, every acquisition segment after the first starts on the last condition that you specified. The Signal Tap Node annotates this final condition column with Seg if a segmented buffer is enabled. The Simple Sequential Triggering feature allows you to specify basic triggers, comparison triggers, advanced triggers, or a mix of all three. The following figure illustrates the simple sequential triggering flow for non-segmented and segmented buffers. The acquisition buffer starts capture when all n triggering levels are satisfied, where n <10.
The Signal Tap logic analyzer considers external triggers as level 0, evaluating external triggers before any other trigger condition.