Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines

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ID 683814
Date 1/14/2022
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Document Table of Contents
Document Table of Contents x
Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines
Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines x
Intel® Arria® 10 GX and GT Pin Connection Guidelines Intel® Arria® 10 SX Pin Connection Guidelines Power Supply Sharing Guidelines for Intel® Arria® 10 Devices Document Revision History for the Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines
Intel® Arria® 10 GX and GT Pin Connection Guidelines x
Clock and PLL Pins Dedicated Configuration/JTAG Pins Optional/Dual-Purpose Configuration Pins Partial Reconfiguration Pins 3V Compatible I/O Pins Differential I/O Pins External Memory Interface and Hard Memory PHY Pins Reference Pins Voltage Sensor Pins Supply Pins Transceiver Pins Notes to Intel® Arria® 10 GX and GT Pin Connection Guidelines
Intel® Arria® 10 SX Pin Connection Guidelines x
HPS Supply Pins HPS Dedicated I/O Bank Pins HPS Peripheral Pins Shared 3V I/O Bank Pins Notes to Intel® Arria® 10 SX Pin Connection Guidelines
Power Supply Sharing Guidelines for Intel® Arria® 10 Devices x
Example 1— Intel® Arria® 10 GX Example 2— Intel® Arria® 10 GX Example 3— Intel® Arria® 10 GX Example 4— Intel® Arria® 10 GT Example 5— Intel® Arria® 10 GT Example 6— Intel® Arria® 10 GT Example 7— Intel® Arria® 10 GT Example 8— Intel® Arria® 10 SX Example 9— Intel® Arria® 10 SX Example 10— Intel® Arria® 10 SX Example 11— Intel® Arria® 10 GX (Using the SmartVID Feature) Notes to Power Supply Sharing Guidelines
Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines

Transceiver Pins

Note: Intel® recommends that you create a Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 11.  Transceiver Pins
Pin Name Pin Functions Pin Description Connection Guidelines
VCCR_GXB[L1,R4] [C,D,E,F,G,H,I,J] Power Analog power, receiver, specific to each transceiver bank of the left (L) side or right (R) side of the device.

Connect VCCR_GXB pins to a 0.95V, 1.03V, or 1.12V low noise switching regulator. 1.12V is applicable only for Intel® Arria® 10 GT devices. For transceivers data rates in respect to each voltage level, refer to the Notes to Power Supply Sharing Guidelines.

If all of the transceivers, fPLLs, and IOPLLs on a side are not used, then the VCCR_GXB power rails of those inner banks on that side can be tied to GND to save power. The two outer banks on either the left or right side must always be powered on for proper operation of the device. The outer banks are always the first bank (lowest alphabetical letter) and last bank (highest alphabetical letter) on a side.

Example 1—Device with 8 transceiver banks on a side.

  • VCCR_GXB1J—left side top outer bank. Do not power down.
  • VCCR_GXB1I
  • VCCR_GXB1H
  • VCCR_GXB1G
  • VCCR_GXB1F
  • VCCR_GXB1E
  • VCCR_GXB1D
  • VCCR_GXB1C—left side bottom outer bank. Do not power down.
  • VCCR_GXB4J—right side top outer bank. Do not power down.
  • VCCR_GXB4I
  • VCCR_GXB4H
  • VCCR_GXB4G
  • VCCR_GXB4F
  • VCCR_GXB4E
  • VCCR_GXB4D
  • VCCR_GXB4C—right side bottom outer bank. Do not power down.

Example 2—Device with 4 transceiver banks on a side.

  • VCCR_GXB1F—left side top outer bank. Do not power down.
  • VCCR_GXB1E
  • VCCR_GXB1D
  • VCCR_GXB1C—left side bottom outer bank. Do not power down.
  • VCCR_GXB4F—right side top outer bank. Do not power down.
  • VCCR_GXB4E
  • VCCR_GXB4D
  • VCCR_GXB4C—right side bottom outer bank. Do not power down.

VCCR_GXB pins on the same side of the device must have the same voltage.

The VCCT_GXB and VCCR_GXB power supplies voltage level must be equivalent if both power supplies are powered on.

See Notes 2, 3, 4, 7, and 10.
VCCT_GXB[L1,R4] [C,D,E,F,G,H,I,J] Power Analog power, transmitter, specific to each transceiver bank of the left (L) side or right (R) side of the device.

Connect VCCT_GXB pins to a 0.95V, 1.03V, or 1.12V low noise switching regulator. 1.12V is applicable only for Intel® Arria® 10 GT devices. For transceivers data rates in respect to each voltage level, refer to the Notes to Power Supply Sharing Guidelines.

If all of the transceivers, fPLLs, and IOPLLs on a side are not used, then the VCCT_GXB power rails on that side can be tied to GND to save power regardless of whether they are an inner or outer bank.

VCCT_GXB pins on the same side of the device must have the same voltage.

The VCCT_GXB and VCCR_GXB power supplies voltage level must be equivalent if both power supplies are powered on.

See Notes 2, 3, 4, 7, and 10.
VCCH_GXB[L,R] Power Analog power, block level transmitter buffers, specific to the left (L) side or right (R) side of the device.

Connect VCCH_GXB to 1.8V low noise switching regulator. With a proper isolation filtering, you have the option to source VCCH_GXB from the same regulator as VCCPT.

All VCCH_GXB of all transceiver banks must be powered on for proper device operation except for the HF34 and NF40 packages of the Intel® Arria® 10 GX and GT devices. For the HF34 and NF40 packages of the Intel® Arria® 10 GX and GT devices, the VCCH_GXBR power rails can be tied to GND to save power if all of the transceivers, fPLLs, and IOPLLs on that side are not used.

VCCH_GXB pins on the same side of the device must have the same voltage.

Provide a minimum decoupling of 2.2nF for the VCCH_GXB power rail near the VCCH_GXB pin.

To reduce voltage regulator module (VRM) switching noise impact on channel jitter performance, the VRM switching frequency for the VCCH_GXB rail should be below 2 MHz. For OTN application, the VRM switching frequency for the VCCH_GXB rail should be below 500 KHz.

See Notes 2, 3, 4, 7, and 10.
GXB[L1,R4][C,D,E,F,G,H,I,J]_RX_[0:5]p , GXB[L,R][1][C,D,E,F,G,H,I,J]_REFCLK_CH[0:5]p Input High speed positive differential receiver channels. Specific to each transceiver bank of the left (L) side or right (R) side of the device. These pins can be AC-coupled or DC-coupled when used. Connect all unused GXB_RXp pins directly to GND, VCCR_GXB, or VCCT_GXB pins.
GXB[L1,R4][C,D,E,F,G,H,I,J]_RX_[0:5]n , GXB[L,R][1][C,D,E,F,G,H,I,J]_REFCLK_CH[0:5]n Input High speed negative differential receiver channels. Specific to each transceiver bank of the left (L) side or right (R) side of the device. These pins can be AC-coupled or DC-coupled when used. Connect all unused GXB_RXn pins directly to GND.
GXB[L1,R4][C,D,E,F,G,H,I,J]_TX_CH[0:5]p Output High speed positive differential transmitter channels. Specific to each transceiver bank of the left (L) side or right (R) side of the device. Leave all unused GXB_TXp pins floating.
GXB[L1,R4][C,D,E,F,G,H,I,J]_TX_CH[0:5]n Output High speed negative differential transmitter channels. Specific to each transceiver bank of the left (L) side or right (R) side of the device. Leave all unused GXB_TXn pins floating.
REFCLK_GXB[L1,R4][C,D,E,F,G,H,I,J]_CH[B,T]p Input

High speed differential reference clock positive receiver channels, specific to each transceiver bank of the left (L) side or right (R) side of the device.

REFCLK_GXB can be used as dedicated clock input pins with fPLL for core clock generation even when the transceiver channel is not available.

These pins must be AC-coupled if the selected REFCLK I/O standard is not HCSL.

In the PCI Express configuration, DC-coupling is allowed on the REFCLK if the selected REFCLK I/O standard is HCSL.

Connect all unused pins either individually to GND or tie all unused pins together through a single 10-kΩ resistor to GND. Ensure that the trace from the pins to the resistor(s) are as short as possible.

See Note 9.
REFCLK_GXB[L1,R4][C,D,E,F,G,H,I,J]_CH[B,T]n Input

High speed differential reference clock complement, complementary receiver channel, specific to each transceiver bank of the left (L) side or right (R) side of the device.

REFCLK_GXB can be used as dedicated clock input pins with fPLL for core clock generation even when the transceiver channel is not available.

These pins must be AC-coupled if the selected REFCLK I/O standard is not HCSL.

In the PCI Express configuration, DC-coupling is allowed on the REFCLK if the selected REFCLK I/O standard is HCSL.

Connect all unused pins either individually to GND or tie all unused pins together through a single 10-kΩ resistor to GND. Ensure that the trace from the pins to the resistor(s) are as short as possible.

See Note 9.
CLKUSR I/O

This pin is used as the clock for transceiver calibration, and is a mandatory requirement when using transceivers. This pin is optionally used for Hybrid Memory Cube (HMC) calibration, as well as a configuration clock input for synchronizing the initialization of more than one device. This is a user-supplied clock and the input frequency range must be in the range from 100 MHz to 125 MHz.

This pin can be used as a GPIO pin only if you are not using transceivers, not using HMC, and not using this pin as a user-supplied configuration clock.

If you are using the CLKUSR pin for configuration and transceiver calibration, you must supply an external free running and stable clock to the CLKUSR pin at start of device configuration and also when the device entered user mode. If the clock is not present at device power-up, transceiver calibration will be delayed until the clock is available. This may impact protocol compliance.

You need to ensure supplying the CLKUSR pin with a common clock frequency that is applicable for both the configuration mode and transceiver calibration.

If you are not using the CLKUSR pin for configuration but using the CLKUSR pin for transceiver calibration, you must supply an external free running and stable clock to the CLKUSR pin at start of device configuration and also when the device entered user mode. If the clock is not present at device power-up, transceiver calibration will be delayed until the clock is available. This may impact protocol compliance.

If you are using the CLKUSR pin for configuration but not using the CLKUSR pin for transceiver calibration, you must use a user-supplied clock input.

For more information, refer to the Configuration, Design Security, and Remote System Upgrades for Intel® Arria® 10 Devices chapter.

Connect the CLKUSR pin to GND if you are not using the CLKUSR pin for any of the following:

  • Configuration clock input
  • Transceiver calibration clock
  • An I/O pin
RREF_[T,B][L,R] Input Reference resistor for fPLL, IOPLL, and transceiver, specific to the top (T) side or bottom (B) side and left (L) side or right (R) side of the device. If any REFCLK pin or transceiver channel on one side (left or right) of the device or IOPLL is used, you must connect each RREF pin on that side of the device to its own individual 2kΩ resistor to GND. Otherwise, you can connect each RREF pin on that side of the device directly to GND. In the PCB layout, the trace from this pin to the resistor needs to be routed so that it avoids any aggressor signals.
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