Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines

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ID 683814
Date 1/14/2022
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Document Table of Contents
Document Table of Contents x
Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines
Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines x
Intel® Arria® 10 GX and GT Pin Connection Guidelines Intel® Arria® 10 SX Pin Connection Guidelines Power Supply Sharing Guidelines for Intel® Arria® 10 Devices Document Revision History for the Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines
Intel® Arria® 10 GX and GT Pin Connection Guidelines x
Clock and PLL Pins Dedicated Configuration/JTAG Pins Optional/Dual-Purpose Configuration Pins Partial Reconfiguration Pins 3V Compatible I/O Pins Differential I/O Pins External Memory Interface and Hard Memory PHY Pins Reference Pins Voltage Sensor Pins Supply Pins Transceiver Pins Notes to Intel® Arria® 10 GX and GT Pin Connection Guidelines
Intel® Arria® 10 SX Pin Connection Guidelines x
HPS Supply Pins HPS Dedicated I/O Bank Pins HPS Peripheral Pins Shared 3V I/O Bank Pins Notes to Intel® Arria® 10 SX Pin Connection Guidelines
Power Supply Sharing Guidelines for Intel® Arria® 10 Devices x
Example 1— Intel® Arria® 10 GX Example 2— Intel® Arria® 10 GX Example 3— Intel® Arria® 10 GX Example 4— Intel® Arria® 10 GT Example 5— Intel® Arria® 10 GT Example 6— Intel® Arria® 10 GT Example 7— Intel® Arria® 10 GT Example 8— Intel® Arria® 10 SX Example 9— Intel® Arria® 10 SX Example 10— Intel® Arria® 10 SX Example 11— Intel® Arria® 10 GX (Using the SmartVID Feature) Notes to Power Supply Sharing Guidelines
Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines

Document Revision History for the Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines

Document Version Changes
2022.01.14 Updated the NAND_RB connection guidelines of the HPS_DEDICATED_12, HPS_Shared_Q2_2, and HPS_Shared_Q4_2 pins.
2021.10.29 Added Table: 3V Compatible I/O Pins.
2020.12.23
Removed the sentence "For better performance and in order to meet PCIe Gen 3 jitter specifications, isolate VCCR_GXB and VCCT_GXB from each other with at least 30 dB of isolation for a 1 MHz to 100 MHz bandwidth." from the following tables:
  • Power Supply Sharing Guidelines for Intel Arria 10 GX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications
  • Power Supply Sharing Guidelines for Intel Arria 10 GX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications
  • Power Supply Sharing Guidelines for Intel Arria 10 GX with Transceiver Data Rate <= 17.4 Gbps(**) for Chip-to-Chip Applications (Transceiver Data Rate <= 12.5 Gbps (**) for Backplane Applications)
  • Power Supply Sharing Guidelines for Intel Arria 10 GT with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications
  • Power Supply Sharing Guidelines for Intel Arria 10 GT with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications
  • Power Supply Sharing Guidelines for Intel Arria 10 GT with Transceiver Data Rate <= 15.0 Gbps (**) for Chip-to-Chip Applications (Transceiver Data Rate <= 12.5 Gbps (**) for Backplane Applications)
  • Power Supply Sharing Guidelines for Intel Arria 10 SX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications
  • Power Supply Sharing Guidelines for Intel Arria 10 SX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications
  • Power Supply Sharing Guidelines for Intel Arria 10 SX with Transceiver Data Rate <= 17.4 Gbps(**) for Chip-to-Chip Applications (Transceiver Data Rate <= 12.5 Gbps (**) for Backplane Applications)
  • Power Supply Sharing Guidelines for Intel Arria 10 GX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications Using the SmartVID Feature
Note: If you have implemented this recommendation on your board and your design functions properly, you do not need to rework the board.
2020.10.20 Updated the connection guidelines for the PR_REQUEST pin.
2019.08.27 Updated the pin description of the CLKUSR pin.
2019.07.01
  • Added reference to the Intel® Arria® 10 Hard Processor System Technical Reference Manual for the Shared 3V I/O Bank Pins section.
  • Updated the connection guidelines of the nIO_PULLUP pin.
  • Updated the definition of HMC in the pin description of the CLKUSR pin.
2018.12.12
  • Updated the connection guidelines for the HPS_Shared_Q2_2 and HPS_Shared_Q4_2 pins.
2018.03.30
  • Added guidelines to avoid excess current on the I/O pins in the Notes to Intel® Arria® 10 GX and GT Pin Connection Guidelines and Notes to Intel® Arria® 10 SX Pin Connection Guidelines sections.
  • Updated the connection guidelines for the nPERST[L,R][0:1] pins to include on the compatible I/O standards.
  • Updated the supported protocols in the pin description for the following pins:
    • CQ[#]
    • CQn[#]
    • CQ[#]_[#]/CQn[#]_[#]
    • QK[#]_[#]
    • QKn[#]_[#]
    • A_[#]
    • BA_[#]
    • REF#
    • WE_N_0
    • CAS_N_0
    • RAS_N_0
    • RPS_N_0
    • WPS_N_0
    • REF_N_0
  • Updated the connection guidelines for the VCCP and VCC pins.
  • Updated the connection guidelines for VCCR_GXB[L1,R4] [C,D,E,F,G,H,I,J] and VCCT_GXB[L1,R4] [C,D,E,F,G,H,I,J] pins.
  • Updated the connection guidelines for VCCH_GXB[L,R] pins to add the VRM switching frequency guidelines.
  • Updated the connection guidelines for the HPS_CLK1 pin to include the hps_clk_f fuse information.
  • Updated the connection guidelines of the HPS_DEDICATED_[4,5,7,8,9,12,13,14,15] pins to include information on the pull-up resistor.
  • Updated the connection guidelines of the HPS_Shared_Q1_[1,2,4,5,6,7,8,9,10,11] and HPS_Shared_Q4_2 pins to include information on the pull-up resistor.
  • Updated the connection guidelines of the BOOTSEL[0..2] pins.
  • Removed the CA_[#]_[#] pins.
Date Version Description of Changes
June 2017 2017.06.16
  • Added note 11 to the Notes to Arria 10 GX and GT Pin Connection Guidelines.
  • Updated the pin functions and connection guidelines for the RZQ_[#] pin.
  • Updated the pin functions for the CLKUSR pin.
  • Added a note for the DisplayPort TX electrical full compliance in the following power sharing guidelines:
    • Example 1. Power Supply Sharing Guidelines for Arria 10 GX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications
    • Example 2. Power Supply Sharing Guidelines for Arria 10 GX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications
    • Example 4. Power Supply Sharing Guidelines for Arria 10 GT with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications
    • Example 5. Power Supply Sharing Guidelines for Arria 10 GT with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications
    • Example 8. Power Supply Sharing Guidelines for Arria 10 SX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications
    • Example 9. Power Supply Sharing Guidelines for Arria 10 SX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications
    • Example 11. Power Supply Sharing Guidelines for Arria 10 GX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications Using the SmartVID Feature (***)
March 2017 2017.03.13 Rebranded as Intel.
December 2016 2016.12.09
  • Updated the connection guidelines for VCCH_GXB[L,R] pins.
  • Updated the connection guidelines for CLK_[2,3] [A,B,C,D,E,F,G,H,I, J,K,L]_[0,1]p and CLK_[2,3] [A,B,C,D,E,F,G,H,I, J,K,L]_[0,1]n pins.
  • Updated the connection guidelines for the RZQ_[#] pin.
  • Updated the connection guidelines for the ALERT_N_0 pin.
June 2016 2016.06.10
  • The document is no longer preliminary.
  • Updated the HPS Peripheral Pins and Shared 3V I/O Bank Pins.
  • Updated the connection guidelines for VCCR_GXB and VCCT_GXB pins.
  • Removed support for the VCC PowerManager feature.
  • Updated note (3) in the Notes to Power Supply Sharing Guidelines.
  • Updated the maximum backplane applications support to 12.5 Gbps.
  • Removed backplane applications support when VCCR_GXB and VCCT_GXB is at 0.95V.
March 2016 2016.03.17 Updated the supported transceiver data rates in the Notes to Power Supply Sharing Guidelines section.
November 2015 2015.11.02
  • Changed instances of Quartus II to Quartus Prime.
  • Updated the connection guidelines of the REFCLK_GXB[L1,R4][C,D,E,F,G,H,I,J]_CH[B,T]p and REFCLK_GXB[L1,R4][C,D,E,F,G,H,I,J]_CH[B,T]n pins.
  • Updated the connection guidelines of the VCCR_GXB[L1,R4] [C,D,E,F,G,H,I,J] pins.
  • Updated the connection guidelines of the VCCT_GXB[L1,R4] [C,D,E,F,G,H,I,J] pins.
  • Updated the connection guidelines of the VCCH_GXB[L,R] pins.
  • Updated the connection guidelines of the CLKUSR pin.
  • Updated the pin type and pin description for the ALERT_N_0, PAR_0, ACT_N_0, and BG_[#0 pins.
  • Updated the connection guidelines of the ADCGND pin.
  • Updated the pin description of the HPS_nRST pin.
  • Updated the pin description of the VCC pin.
  • Updated the connection guidelines of the nIO_PULLUP pin.
  • Updated the connection guidelines of the VCCLSENSE and GNDSENSE pins.
  • Updated the minimum voltage to 0.95V in the connection guidelines of the VCCR_GXB[L1,R4] [C,D,E,F,G,H,I,J] and VCCT_GXB[L1,R4] [C,D,E,F,G,H,I,J] pins.
  • Updated the following power sharing guidelines to include 0.95V and 1.12V support for VCCR_GXB[L1,R4] [C,D,E,F,G,H,I,J] and VCCT_GXB[L1,R4] [C,D,E,F,G,H,I,J]:
    • Example 1. Power Supply Sharing Guidelines for Arria 10 GX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications (10.3125 Gbps for Backplane Applications)
    • Example 2. Power Supply Sharing Guidelines for Arria 10 GX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications (10.3125 Gbps for Backplane Applications)
    • Example 4. Power Supply Sharing Guidelines for Arria 10 GT with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications (10.3125 Gbps for Backplane Applications)
    • Example 5. Power Supply Sharing Guidelines for Arria 10 GT with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications (10.3125 Gbps for Backplane Applications)
    • Example 7. Power Supply Sharing Guidelines for Arria 10 GT with 15.0 Gbps < Transceiver Data Rate <= 17.4 Gbps(**)/28.3 Gbps for Chip-to-Chip Applications (14.2 Gbps < Transceiver Data Rate <= 17.4 Gbps(**) for Backplane Applications)
    • Example 8. Power Supply Sharing Guidelines for Arria 10 SX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications (10.3125 Gbps for Backplane Applications)
    • Example 9. Power Supply Sharing Guidelines for Arria 10 SX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications (10.3125 Gbps for Backplane Applications)
    • Example 11. Power Supply Sharing Guidelines for Arria 10 GX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications (10.3125 Gbps for Backplane Applications) Using the SmartVID Feature (***)
April 2015 2015.04.05
  • Updated the connection guidelines of VCCP and VCC pins.
  • Updated the connection guidelines of RREF [T,B][L,R] pins.
  • Updated the connection guidelines of nPERST[L,R][0:1] pins.
  • Updated the connection guidelines of the VREFP_ADC pins.
  • Updated the connection guidelines of the VCCERAM pin.
  • Updated the connection guidelines of VREFB[[2][A,F,G,H,I,J,K,L],[3][A,B,C,D,E,F,G,H]]N0 pins.
  • Updated the on-chip reference source to ±10% in the connection guidelines of the VREFP_ADC pin.
  • Updated the supported nominal voltage of VCCR_GXB[L1,R4][C,D,E,F,G,H,I,J] and VCCT_GXB[L1,R4][C,D,E,F,G,H,I,J] from 1.0V and 1.1V to 1.03V and 1.11V, respectively.
    • Updated the connection guidelines for VCCR_GXB[L1,R4][C,D,E,F,G,H,I,J] and VCCT_GXB[L1,R4][C,D,E,F,G,H,I,J].
    • Updated the following power sharing guidelines for the supported nominal voltage of 1.03V and 1.11V for VCCR_GXB[L1,R4][C,D,E,F,G,H,I,J] and VCCT_GXB[L1,R4][C,D,E,F,G,H,I,J]:
      • Example 3. Power Supply Sharing Guidelines for Arria 10 GX with 11.3 Gbps < Transceiver Data Rate <= 17.4 Gbps(**) for Chip-to-Chip Applications (10.3125 Gbps <Transceiver Data Rate <= 17.4 Gbps (**) for Backplane Applications)
      • Example 6. Power Supply Sharing Guidelines for Arria 10 GT with 11.3 Gbps < Transceiver DataRate <= 15.0 Gbps(**) for Chip-to-Chip Applications (10.3125 Gbps < Transceiver Data Rate <= 14.2 Gbps(**) for Backplane Applications)
      • Example 7. Power Supply Sharing Guidelines for Arria 10 GT with 15.0 Gbps < Transceiver Data Rate <= 17.4 Gbps(**)/28.3 Gbps for Chip-to-Chip Applications (14.2 Gbps < Transceiver Data Rate <= 17.4 Gbps(**) for Backplane Applications)
      • Example 10. Power Supply Sharing Guidelines for Arria 10 SX with 11.3 Gbps < Transceiver Data Rate <= 17.4 Gbps(**) for Chip-to-Chip Applications (10.3125 Gbps <Transceiver Data Rate <= 17.4 Gbps (**) for Backplane Applications)
    • Updated the supported nominal voltage of 1.03V and 1.11V for VCCR_GXB[L1,R4][C,D,E,F,G,H,I,J] and VCCT_GXB[L1,R4][C,D,E,F,G,H,I,J] in the Notes to Power Supply Sharing Guidelines.
  • Added Shared 3V I/O Bank pins for Arria 10 HPS.
January 2015 2015.01.23
  • Updated the connection guidelines for VCCIO([2][A, F,G,H,I,J,K, L, AF, KL], [3][A, B,C,D,E,F,G, H, AB, GH]) pins.
  • Updated the connection guidelines for the CONF_DONE pin.
  • Updated the connection guidelines for the nSTATUS pin.
  • Updated the connection guidelines for VREFP_ADC and VREFN_ADC pins.
  • Updated the pin type for VSIGP and VSIGN pins.
  • Updated the pin type for the HPS_nRST pin.
  • Updated the pin type for the HPS_nPOR pin.
  • Updated the pin description of the CRC_ERROR pin.
  • Updated the pin description of the HPS_nRST pin.
  • Updated the connection guidelines for VCCT_GXB[L1,R4] [C,D,E,F,G,H,I,J] and VCCR_GXB[L1,R4][C,D,E,F,G,H,I,J] pins.
  • Updated the pin description for VCCIOREF_HPS pin.
  • Updated note (11) in the Notes to Arria 10 SX Pin Connection Guidelines.
  • Updated the following power sharing guidelines to include 0.95V support for VCC and VCCP:
    • Example 1. Power Supply Sharing Guidelines for Arria 10 GX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications (10.3125 Gbps for Backplane Applications)
    • Example 3. Power Supply Sharing Guidelines for Arria 10 GX with 11.3 Gbps < Transceiver Data Rate <= 17.4 Gbps(**) for Chip-to-Chip Applications (10.3125 Gbps <Transceiver Data Rate <= 17.4 Gbps (**) for Backplane Applications)
    • Example 4. Power Supply Sharing Guidelines for Arria 10 GT with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications (10.3125 Gbps for Backplane Applications)
    • Example 6. Power Supply Sharing Guidelines for Arria 10 GT with 11.3 Gbps < Transceiver Data Rate <= 15.0 Gbps(**) for Chip-to-Chip Applications (10.3125 Gbps < Transceiver Data Rate <= 14.2 Gbps(**) for Backplane Applications)
    • Example 7. Power Supply Sharing Guidelines for Arria 10 GT with 15.0 Gbps < Transceiver Data Rate <= 17.4 Gbps(**)/28.3 Gbps for Chip-to-Chip Applications (14.2 Gbps < Transceiver Data Rate <= 17.4 Gbps(**) for Backplane Applications)
    • Example 8. Power Supply Sharing Guidelines for Arria 10 SX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications (10.3125 Gbps for Backplane Applications)
    • Example 10. Power Supply Sharing Guidelines for Arria 10 SX with 11.3 Gbps < Transceiver Data Rate <= 17.4 Gbps(**) for Chip-to-Chip Applications (10.3125 Gbps <Transceiver Data Rate <= 17.4 Gbps (**) for Backplane Applications)
  • Added the following power sharing guidelines:
    • Example 2. Power Supply Sharing Guidelines for Arria 10 GX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications (10.3125 Gbps for Backplane Applications)
    • Example 5. Power Supply Sharing Guidelines for Arria 10 GT with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications (10.3125 Gbps for Backplane Applications)
    • Example 9. Power Supply Sharing Guidelines for Arria 10 SX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications (10.3125 Gbps for Backplane Applications)
August 2014 2014.08.18
  • Added Example 8. Power Supply Sharing Guidelines for Arria 10 GX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications (10.3125 Gbps for Backplane Applications) Using the SmartVID Feature.
  • Updated the transceiver data rate to 28.3 Gbps.
  • Updated the pin name and pin description of the PLL_[2,3][A,B,C,D,E,F,G,H,I,J,K,L]_FB[0,1] pins.
  • Updated the connection guidelines for the TCK, TMS, TDI, TDO, and TRST pins.
  • Updated the pin name and connection guidelines of the CRC_ERROR pin.
  • Updated the connection guidelines of the nPERST[L,R][0:1] pins.
  • Updated the connection guidelines of the VREFP_ADC pin.
  • Updated the connection guidelines of the VSIGP_[0,1] and VSIGN_[0,1] pins.
  • Updated the connection guidelines of the VCCP and VCC pins.
  • Updated the pin name of the VCCIO([2][A,F,G,H,I,J,K,L,AF,KL],[3][A,B,C,D,E,F,G,H,AB,GH]) pins.
  • Updated the connection guidelines of the VCCERAM pins.
  • Updated the connection guidelines of the VREFB([2][A,F,G,H,I,J,K,L],[3][A,B,C,D,E,F,G,H])N0 pins.
  • Updated the connection guidelines of the VCCLSENSE and GNDSENSE pins.
  • Updated the connection guidelines for the ADCGND pin.
  • Updated the pin name, pin description, and connection guidelines of the VCCR_GXB[L1,R4] [C,D,E,F,G,H,I,J] pins.
  • Updated the pin name, pin description, and connection guidelines of the VCCT_GXB[L1,R4] [C,D,E,F,G,H,I,J] pins.
  • Updated the pin description and connection guidelines of the VCCH_GXB[L,R] pins.
  • Updated the pin name and pin description of the GXB[L1,R4][C,D,E,F,G,H,I,J]_RX_[0:5]p, GXB[L1,R4][C,D,E,F,G,H,I,J]_RX_[0:5]n, GXB[L1,R4][C,D,E,F,G,H,I,J]_TX_CH[0:5]p, GXB[L1,R4][C,D,E,F,G,H,I,J]_TX_CH[0:5]n pins.
  • Updated the pin name, pin description, and connection guidelines for the REFCLK_GXB[L1,R4][C,D,E,F,G,H,I,J]_CH[B,T]p and REFCLK_GXB[L1,R4][C,D,E,F,G,H,I,J]_CH[B,T]n pins.
  • Updated the connection guidelines of the CLKUSR pins.
  • Updated the pin description and connection guidelines for the RREF_[T,B][L,R] pins.
  • Updated the Function 2 pin description of the HPS_DEDICATED_16 pin.
June 2014 2014.06.24
  • Added note (7) to the Notes to Power Supply Sharing Guidelines section.
  • Updated the pin description for the PLL_[2,3][A,B,C,D,E,F,G,H,I,J,K,L]_FB0 pins.
  • Updated the connection guidelines for the TCK, TMS, TDI, TDO, and TRST pins.
  • Updated the connection guidelines for the VCCR_GXB[L,R][1:4][C,D,E,F,G,H,I,J] and VCCT_GXB[L,R][1:4][C,D,E,F,G,H,I,J] pins.
  • Updated the connection guidelines for the VCCLSENSE and GNDSENSE pins.
  • Updated the connection guidelines for the VCCBAT, VCCPGM, VCCPT, and VCCH_GXB[L,R] pins.
  • Updated the CRCERROR pin name.
  • Updated the following power sharing guidelines:
    • Example 1. Power Supply Sharing Guidelines for Arria 10 GX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications (10.3125 Gbps for Backplane Applications)
    • Example 2. Power Supply Sharing Guidelines for Arria 10 GX with Transceiver Data Rate 11.3 Gbps < Data Rates <= 17.4 Gbps(**) for Chip-to-Chip Applications (10.3125 Gbps <Data Rates <= 17.4 Gbps (**) for Backplane Applications)
    • Example 3. Power Supply Sharing Guidelines for Arria 10 GT with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications (10.3125 Gbps for Backplane Applications)
    • Example 4. Power Supply Sharing Guidelines for Arria 10 GT with Transceiver Data Rate 11.3 Gbps < Data Rates <= 15.0 Gbps(**) for Chip-to-Chip Applications (10.3125 Gbps < Data Rates <= 14.2 Gbps(**) for Backplane Applications)
    • Example 5. Power Supply Sharing Guidelines for Arria 10 GT with Transceiver Data Rate 15.0 Gbps < Data Rates <= 17.4 Gbps(**)/28 Gbps for Chip-to-Chip Applications (14.2 Gbps < Data Rates <= 17.4 Gbps(**) for Backplane Applications)
    • Example 6. Power Supply Sharing Guidelines for Arria 10 SX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications (10.3125 Gbps for Backplane Applications)
    • Example 7. Power Supply Sharing Guidelines for Arria 10 SX with Transceiver Data Rate 11.3 Gbps < Data Rates <= 17.4 Gbps(**) for Chip-to-Chip Applications (10.3125 Gbps <Data Rates <= 17.4 Gbps (**) for Backplane Applications)
May 2014 2014.05.23 Updated the pin description and connection guidelines for the CLKUSR pin.
December 2013 2013.12.18 Updated the connection guidelines for VCC and VCCP pins.
December 2013 2013.12.02 Initial release.
Level Two Title