Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines
ID
683814
Date
7/23/2025
Public
Visible to Intel only — GUID: wtw1461056289516
Ixiasoft
1.1.1. Clock and PLL Pins
1.1.2. Dedicated Configuration/JTAG Pins
1.1.3. Optional/Dual-Purpose Configuration Pins
1.1.4. Partial Reconfiguration Pins
1.1.5. 3V Compatible I/O Pins
1.1.6. Differential I/O Pins
1.1.7. External Memory Interface and Hard Memory PHY Pins
1.1.8. Reference Pins
1.1.9. Voltage Sensor Pins
1.1.10. Supply Pins
1.1.11. Transceiver Pins
1.1.12. Notes to Arria® 10 GX and GT Pin Connection Guidelines
1.3.1. Example 1— Arria® 10 GX
1.3.2. Example 2— Arria® 10 GX
1.3.3. Example 3— Arria® 10 GX
1.3.4. Example 4— Arria® 10 GT
1.3.5. Example 5— Arria® 10 GT
1.3.6. Example 6— Arria® 10 GT
1.3.7. Example 7— Arria® 10 GT
1.3.8. Example 8— Arria® 10 SX
1.3.9. Example 9— Arria® 10 SX
1.3.10. Example 10— Arria® 10 SX
1.3.11. Example 11— Arria® 10 GX (Using the SmartVID Feature)
1.3.12. Notes to Power Supply Sharing Guidelines
Visible to Intel only — GUID: wtw1461056289516
Ixiasoft
1.1. Arria® 10 GX and GT Pin Connection Guidelines
Section Content
Clock and PLL Pins
Dedicated Configuration/JTAG Pins
Optional/Dual-Purpose Configuration Pins
Partial Reconfiguration Pins
3V Compatible I/O Pins
Differential I/O Pins
External Memory Interface and Hard Memory PHY Pins
Reference Pins
Voltage Sensor Pins
Supply Pins
Transceiver Pins
Notes to Arria 10 GX and GT Pin Connection Guidelines