Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines

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ID 683814
Date 1/14/2022
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Document Table of Contents x
Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines
Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines x
Intel® Arria® 10 GX and GT Pin Connection Guidelines Intel® Arria® 10 SX Pin Connection Guidelines Power Supply Sharing Guidelines for Intel® Arria® 10 Devices Document Revision History for the Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines
Intel® Arria® 10 GX and GT Pin Connection Guidelines x
Clock and PLL Pins Dedicated Configuration/JTAG Pins Optional/Dual-Purpose Configuration Pins Partial Reconfiguration Pins 3V Compatible I/O Pins Differential I/O Pins External Memory Interface and Hard Memory PHY Pins Reference Pins Voltage Sensor Pins Supply Pins Transceiver Pins Notes to Intel® Arria® 10 GX and GT Pin Connection Guidelines
Intel® Arria® 10 SX Pin Connection Guidelines x
HPS Supply Pins HPS Dedicated I/O Bank Pins HPS Peripheral Pins Shared 3V I/O Bank Pins Notes to Intel® Arria® 10 SX Pin Connection Guidelines
Power Supply Sharing Guidelines for Intel® Arria® 10 Devices x
Example 1— Intel® Arria® 10 GX Example 2— Intel® Arria® 10 GX Example 3— Intel® Arria® 10 GX Example 4— Intel® Arria® 10 GT Example 5— Intel® Arria® 10 GT Example 6— Intel® Arria® 10 GT Example 7— Intel® Arria® 10 GT Example 8— Intel® Arria® 10 SX Example 9— Intel® Arria® 10 SX Example 10— Intel® Arria® 10 SX Example 11— Intel® Arria® 10 GX (Using the SmartVID Feature) Notes to Power Supply Sharing Guidelines
Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines

Partial Reconfiguration Pins

Note: Intel® recommends that you create a Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 4.  Partial Reconfiguration Pins
Pin Name Pin Functions Pin Description Connection Guidelines
PR_REQUEST I/O, Input

Partial reconfiguration request pin.

Drive this pin high to start partial reconfiguration. Drive this pin low to end reconfiguration.

You can only use this pin in partial reconfiguration using an external host mode in FPP x16 configuration scheme.

Leaving the PR_REQUEST pin floating may cause configuration error. Drive this pin low during configuration whether you use this pin as a partial reconfiguration pin.

This pin is reserved as an input with a weak pull-up during configuration. When you do not use this pin as the dedicated input PR_REQUEST pin, and when this pin is not used as an I/O pin, tie this pin to GND.

You can use the PR_REQUEST pin as an I/O pin. If this pin is used as input pin, the host or external component connected to this pin must drive this pin low during device configuration.

PR_READY I/O, Output or Output (open-drain) The partial reconfiguration ready pin is driven low until the device is ready to begin partial reconfiguration. When the device is ready to start reconfiguration, this signal is released and pulled high by an external pull-up resistor.

When you use as optionally open-drain output dedicated PR_READY pin, connect this pin to an external 10-kΩ pull-up resistor to VCCPGM.

When you do not use as the dedicated PR_READY optionally open-drain output, and when this pin is not used as an I/O pin, connect this pin as defined in the Intel® Quartus® Prime software.

PR_ERROR I/O, Output or Output (open-drain) The partial reconfiguration error pin is driven low during partial reconfiguration unless the device detects an error. If an error is detected, this signal is released and pulled high by an external pull-up resistor.

When you use as optionally open-drain output dedicated PR_ERROR pin, connect this pin to an external 10-kΩ pull-up resistor to VCCPGM.

When you do not use as the dedicated PR_ERROR optionally open-drain output, and when this pin is not used as an I/O pin, connect this pin as defined in the Intel® Quartus® Prime software.

PR_DONE I/O, Output or Output (open-drain) The partial reconfiguration done pin is driven low until the partial reconfiguration is complete. When the reconfiguration is complete, this signal is released and pulled high by an external pull-up resistor.

When you use as optionally open-drain output dedicated PR_DONE pin, connect this pin to an external 10-kΩ pull-up resistor to VCCPGM.

When you do not use as the dedicated PR_DONE optionally open-drain output, and when this pin is not used as an I/O pin, connect this pin as defined in the Intel® Quartus® Prime software.

CvP_CONFDONE I/O, Output (open-drain)

CvP done pin is driven low during configuration. When the CvP configuration is complete, this signal is released and pulled high by an external pull-up resistor.

Status of this pin is only valid if the CONF_DONE pin is high.

When you use as optionally open-drain output dedicated CvP_CONFDONE pin, connect this pin to an external 10-kΩ pull-up resistor to VCCPGM.

When you do not use as the dedicated CvP_CONFDONE optionally open-drain output, and when this pin is not used as an I/O pin, connect this pin as defined in the Intel® Quartus® Prime software.

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