Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide

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ID 683788
Date 10/08/2019
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide 2. Developing an Intel Arria 10 SoC Custom Platform 3. Building the Software and SD Card Image for the Intel® Arria® 10 SoC Development Kit Reference Platform 4. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide Archives 5. Document Revision History for Intel® FPGA SDK for OpenCL™ : Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide
1. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide x
1.1. Intel Arria 10 SoC Development Kit Reference Platform: Prerequisites 1.2. Features of the Intel Arria 10 SoC Development Kit Reference Platform 1.3. Intel Arria 10 SoC Development Kit Reference Platform Board Variants 1.4. Contents of the Intel Arria 10 SoC Development Kit Reference Platform 1.5. Changes in Intel Arria 10 SoC Development Kit Reference Platform from 17.0 to 17.1 1.6. Changes in Intel Arria 10 SoC Development Kit Reference Platform from 17.1.2 to 18.0
2. Developing an Intel Arria 10 SoC Custom Platform x
2.1. Initializing an Intel Arria 10 SoC Custom Platform 2.2. Modifying Your Intel Arria 10 SoC Custom Platform 2.3. Integrating Your Intel Arria 10 SoC Custom Platform with the Intel® FPGA SDK for OpenCL™ 2.4. Changing the Device Part Number 2.5. Modifying the Kernel PLL Reference Clock 2.6. Modifying the Hard Processor System 2.7. Guaranteeing Timing Closure in the Intel Arria 10 SoC Custom Platform 2.8. Generating the base.qar Post-Fit Netlist for Your Intel Arria 10 SoC FPGA Custom Platform
3. Building the Software and SD Card Image for the Intel® Arria® 10 SoC Development Kit Reference Platform x
3.1. Compiling the Device Tree Blob 3.2. Compiling the Linux Kernel for the Intel Arria 10 SoC Development Kit 3.3. Compiling the OpenCL Linux Kernel Driver 3.4. Generating Full-Chip Programming File for SD Card Image 3.5. Building the SD Card Image 3.6. Known Issues
3.5. Building the SD Card Image x
3.5.1. Layout of the OpenCL Micro SD Card 3.5.2. Creating the SD Card Image 3.5.3. Guidelines on Imaging the Micro SD Card
3.5.2. Creating the SD Card Image x
3.5.2.1. Creating Partition 1 of the SD Card Image 3.5.2.2. Creating Partition 2 of the SD Card Image 3.5.2.3. Creating Partition 3 of the SD Card Image
1. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide
2. Developing an Intel Arria 10 SoC Custom Platform
3. Building the Software and SD Card Image for the Intel® Arria® 10 SoC Development Kit Reference Platform
4. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide Archives
5. Document Revision History for Intel® FPGA SDK for OpenCL™ : Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide

3.1. Compiling the Device Tree Blob

You must compile the device tree blob contained in the FAT partition to match your Intel® Arria® 10 SoC Development Kit Reference Platform. Use the Device Tree Generator (sopc2dts) and the Device Tree Compiler (dtc) to generate the necessary device tree blob.
For detailed information on how to generate the device tree blob, refer to Rocketboards.org.
  1. Run base revision compile (aoc -bsp-flow=base) with your a10soc development kit BSP in the following location: 
    $INTELFPGAOCLSDKROOT/board/a10soc
  2. Start an Embedded Command Shell and navigate to the Quartus project directory from your base revision compile.
  3. Invoke the following command to generate the .dts Device Tree file, which is a text representation of the Device Tree: 
    sopc2dts --input board/board.sopcinfo  \
--output a10soc.dts  \
--board hps_a10_common_board_info.xml \
--board hps_a10_devkit_board_info.xml \
--board qsys_top_board_info.xml \
--bridge-removal all --clocks

    The board.sopcinfo file is generated during the base revision compilation of your FPGA design. You may download the XML files from the Intel® Arria® 10 GHRD on Rocketboards.org.

    Attention: Ensure that the name of the Intel® Arria® 10 Hard Processor System in your board.qsys file matches the name used in Intel® Arria® 10 GHRD project you are downloading the XML files from. At the time this document was written, the name of the Intel® Arria® 10 Hard Processor System in board.qsys and in Intel® Arria® 10 GHRD project was a10_hps.

    Create your copy of the Intel® Arria® 10 SoC BSP from the SDK, and rename the instance of the Intel® Arria® 10 Hard Processor System in board.qsys to a10_hps.

  4. After you generate the .dts file, modify its contents by performing the following tasks:
    1. In the Device Tree (a10soc.dts), change the compatible field setting to altr, socfpga. 
      board_irq_ctrl_0: unknown@0x10000cfa0 {
       compatible = "altr,socfpga";

       reg = <0x00000001 0x0000cfa0 0x00000004>,
             <0x00000001 0x0000cf90 0x00000004>;
       reg-names = "IRQ_Mask_Slave", "IRQ_Read_Slave";
       interrupt-parent = <&a10_hps_arm_gic_0>;
       interrupts = <0 19 4>;
       interrupt-controller;
       #interrupt-cells = <1>;
       clocks = <&config_clk>;
}; //end unknown@0x10000cfa0 (board_irq_ctrl_0)
      Note:

      The compatible field setting in a10soc.dts must match the driver code in aclsoc.c. If the two strings do not match, the driver installation process does not allow the kernel to probe the device. As a result, the interrupt is not registered and the host code fails.

      Code snippet in the aclsoc.c file: 

      static const struct of_device_id aclsoc_of_match[] = {
     { .compatible = "altr,socfpga", },
     { /* end of list */ },
};
  5. After you modify the .dts file and it is ready to probed by the platform driver, compile the device tree blob by invoking the following Device Tree Compiler command:
    dtc -f -I dts -O dtb –o a10soc.dtb a10soc.dts

    This command generates the a10soc.dtb file.

  6. Rename the a10soc.dtb file to socfpga_arria10_socdk_sdmmc.dtb.
    The socfpga_arria10_socdk_sdmmc.dtb file is needed later in Building the SD Card Image.
  7. If you modify any of the HPS settings in the design, you must regenerate the uboot.
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