AN 839: Design Block Reuse Tutorial: for Intel® Arria® 10 FPGA Development Board

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ID 683783
Date 7/26/2019
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1. AN 839: Design Block Reuse Tutorial for Intel® Arria® 10 FPGA Development Board
1. AN 839: Design Block Reuse Tutorial for Intel® Arria® 10 FPGA Development Board x
1.1. Tutorial Overview 1.2. Tutorial Software and Hardware 1.3. Tutorial Files 1.4. Core Partition Reuse—Developer Tutorial 1.5. Core Partition Reuse—Consumer Tutorial 1.6. Root Partition Reuse—Developer Tutorial 1.7. Root Partition Reuse—Consumer Tutorial 1.8. (Optional) Step 8: Device Programming 1.9. AN 839: Design Block Reuse Tutorial Document Revision History
1.4. Core Partition Reuse—Developer Tutorial x
1.4.1. Step 1: Define a Core Partition 1.4.2. Step 2: Compile and Export the Core Partition 1.4.3. Step 3: Create the Black Box File 1.4.4. Step 4: Copy Files to Consumer Project 1.4.5. Step 5: Hardware Verification (Optional)
1.5. Core Partition Reuse—Consumer Tutorial x
1.5.1. Step 1: Add Files and Run Synthesis 1.5.2. Step 2: Create a Partition for blinking_led 1.5.3. Step 3: Compile the Design 1.5.4. Step 4: Hardware Verification (Optional)
1.6. Root Partition Reuse—Developer Tutorial x
1.6.1. Step 1: Create a Reserved Core Partition 1.6.2. Step 2: Define a Logic Lock Region 1.6.3. Step 3: Compile and Export the Root Partition 1.6.4. Step 4: Copy Files to Consumer Project 1.6.5. Step 5: Hardware Verification (Optional)
1.7. Root Partition Reuse—Consumer Tutorial x
1.7.1. Step 1: Add the SDC and Root Partition 1.7.2. Step 2: Compile the Design 1.7.3. Step 3: Hardware Verification (Optional)
1. AN 839: Design Block Reuse Tutorial for Intel® Arria® 10 FPGA Development Board

1.6.2. Step 2: Define a Logic Lock Region

You must define a core-only, reserved, fixed routing region to reserve core resources in the Consumer project for the reserved core partition. The Consumer uses this area for core logic development.

Ensure that the exclusive placement region size is large enough to contain all core logic in the reserved core partition. For projects with multiple core partitions, constrain each partition in a non-overlapping placement or routing region. Follow these steps to define a core-only, reserved, fixed routing region to reserve core resources in the Developer project for non-periphery development:

  1. Right-click the u_blinking_led instance in the Project Navigator and click Logic Lock Region > Create New Logic Lock Region.
  2. To modify the region properties, click Assignments > Logic Lock Regions Window.
  3. In the Origin column, specify X63_Y102.
  4. Change the Width to 123, and the Height to 61.
  5. Enable the Reserved and Core-Only options.
  6. Click the Routing Region cell. The Logic Lock Routing Region Settings dialog box appears.
  7. Specify Fixed with expansion with Expansion Length of 0 for the Routing Type. The actual size and location are arbitrary for this tutorial. However, you can view and adjust the Logic Lock Region shape in the Chip Planner.
    Figure 18.  Logic Lock Regions Window
  8. In the Logic Lock Regions window, right-click the u_blinking_led Logic Lock region name, and then click Locate Node > Locate in Chip Planner.

The Logic Lock region is shaded in purple. Preserving the periphery requires exporting everything outside the Logic Lock region. This is the reverse of the core partition reuse flow.

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