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1. Intel® Agilex™ 7 F-Series and I-Series General-Purpose I/O Overview
2. Intel® Agilex™ 7 F-Series and I-Series GPIO Banks
3. Intel® Agilex™ 7 F-Series and I-Series HPS I/O Banks
4. Intel® Agilex™ 7 F-Series and I-Series SDM I/O Banks
5. Intel® Agilex™ 7 F-Series and I-Series I/O Troubleshooting Guidelines
6. Intel® Agilex™ 7 F-Series and I-Series General-Purpose I/O IPs
7. Programmable I/O Features Description
8. Documentation Related to the Intel® Agilex™ 7 General-Purpose I/O User Guide: F-Series and I-Series
9. Document Revision History for the Intel® Agilex™ 7 General-Purpose I/O User Guide: F-Series and I-Series
2.5.1. VREF Sources and VREF Pins
2.5.2. I/O Standards Implementation Based on VCCIO_PIO Voltages
2.5.3. OCT Calibration Block Requirement
2.5.4. I/O Pins Placement Requirements
2.5.5. I/O Standard Selection and I/O Bank Supply Compatibility Check
2.5.6. Simultaneous Switching Noise
2.5.7. Special Pins Requirement
2.5.8. External Memory Interface Pin Placement Requirements
2.5.9. HPS Shared I/O Requirements
2.5.10. Clocking Requirements
2.5.11. SDM Shared I/O Requirements
2.5.12. Unused Pins
2.5.13. Voltage Setting for Unused GPIO Banks
2.5.14. GPIO Pins During Power Sequencing
2.5.15. Drive Strength Requirement for GPIO Input Pins
2.5.16. Maximum DC Current Restrictions
2.5.17. 1.2 V I/O Interface Voltage Level Compatibility
2.5.18. GPIO Pins for the Avalon® Streaming Interface Configuration Scheme
2.5.19. Maximum True Differential Signaling Receiver Pairs Per I/O Lane
6.1.1. Release Information for GPIO Intel® FPGA IP
6.1.2. Generating the GPIO Intel® FPGA IP
6.1.3. GPIO Intel® FPGA IP Parameter Settings
6.1.4. GPIO Intel® FPGA IP Interface Signals
6.1.5. GPIO Intel® FPGA IP Architecture
6.1.6. Verifying Resource Utilization and Design Performance
6.1.7. GPIO Intel® FPGA IP Timing
6.1.8. GPIO Intel® FPGA IP Design Examples
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2.5.12. Unused Pins
There are specific guidelines for unused pins connections and reserved state settings. To allow flexibility in the board design, F-Series and I-Series devices support several options of reserved state settings.
Pin | Guidelines |
---|---|
No connect (NC) pins | For vertical device migration, where the device package is the same but contains different density, you can leave the NC pins floating, connected to VCCIO, or connected to ground. The device pin-out files list the NC pins. |
Do not use (DNU) pins | Do not connect DNU pins to power, ground, or any other signal. You must leave the DNU pins floating. |
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