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1. Intel® Agilex™ 7 F-Series and I-Series General-Purpose I/O Overview
2. Intel® Agilex™ 7 F-Series and I-Series GPIO Banks
3. Intel® Agilex™ 7 F-Series and I-Series HPS I/O Banks
4. Intel® Agilex™ 7 F-Series and I-Series SDM I/O Banks
5. Intel® Agilex™ 7 F-Series and I-Series I/O Troubleshooting Guidelines
6. Intel® Agilex™ 7 F-Series and I-Series General-Purpose I/O IPs
7. Programmable I/O Features Description
8. Documentation Related to the Intel® Agilex™ 7 General-Purpose I/O User Guide: F-Series and I-Series
9. Document Revision History for the Intel® Agilex™ 7 General-Purpose I/O User Guide: F-Series and I-Series
2.5.1. VREF Sources and VREF Pins
2.5.2. I/O Standards Implementation Based on VCCIO_PIO Voltages
2.5.3. OCT Calibration Block Requirement
2.5.4. I/O Pins Placement Requirements
2.5.5. I/O Standard Selection and I/O Bank Supply Compatibility Check
2.5.6. Simultaneous Switching Noise
2.5.7. Special Pins Requirement
2.5.8. External Memory Interface Pin Placement Requirements
2.5.9. HPS Shared I/O Requirements
2.5.10. Clocking Requirements
2.5.11. SDM Shared I/O Requirements
2.5.12. Unused Pins
2.5.13. Voltage Setting for Unused GPIO Banks
2.5.14. GPIO Pins During Power Sequencing
2.5.15. Drive Strength Requirement for GPIO Input Pins
2.5.16. Maximum DC Current Restrictions
2.5.17. 1.2 V I/O Interface Voltage Level Compatibility
2.5.18. GPIO Pins for the Avalon® Streaming Interface Configuration Scheme
2.5.19. Maximum True Differential Signaling Receiver Pairs Per I/O Lane
6.1.1. Release Information for GPIO Intel® FPGA IP
6.1.2. Generating the GPIO Intel® FPGA IP
6.1.3. GPIO Intel® FPGA IP Parameter Settings
6.1.4. GPIO Intel® FPGA IP Interface Signals
6.1.5. GPIO Intel® FPGA IP Architecture
6.1.6. Verifying Resource Utilization and Design Performance
6.1.7. GPIO Intel® FPGA IP Timing
6.1.8. GPIO Intel® FPGA IP Design Examples
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4.2.3. I/O Standards and Features for Configuration Pins
The SDM pins have different I/O standards and features in different configuration schemes. You can assign the unused SDM pins for other functions in the Intel® Quartus® Prime software.
Pin Function | SDM I/O | Direction | I/O Standard | Schmitt Trigger/TTL Input | Weak Pull-Up/Pull-Down | Drive Strength | Open Drain | Slew Rate |
---|---|---|---|---|---|---|---|---|
AS_DATA1 | SDM_IO1 | Bidirectional | 1.8 V LVCMOS | Schmitt Trigger | Disable | 8 mA | Disable | Fast |
AS_CLK | SDM_IO2 | Output | 1.8 V LVCMOS | — | — | 8 mA | Disable | Fast |
AS_DATA2 | SDM_IO3 | Bidirectional | 1.8 V LVCMOS | Schmitt Trigger | Disable | 8 mA | Disable | Fast |
AS_DATA0 | SDM_IO4 | Bidirectional | 1.8 V LVCMOS | Schmitt Trigger | Disable | 8 mA | Disable | Fast |
AS_nCSO0 | SDM_IO5 | Output | 1.8 V LVCMOS | — | — | 8 mA | Disable | Fast |
AS_DATA3 | SDM_IO6 | Bidirectional | 1.8 V LVCMOS | Schmitt Trigger | Disable | 8 mA | Disable | Fast |
AS_nCSO2 | SDM_IO7 | Output | 1.8 V LVCMOS | — | — | 8 mA | Disable | Fast |
AS_nCSO3 | SDM_IO8 | Output | 1.8 V LVCMOS | — | — | 8 mA | Disable | Fast |
AS_nCSO1 | SDM_IO9 | Output | 1.8 V LVCMOS | — | — | 8 mA | Disable | Fast |
AS_nRST | SDM_IO15 | Output | 1.8 V LVCMOS | — | — | 8 mA | Disable | Fast |
SDM I/O | Direction | I/O Standard | Schmitt Trigger/TTL Input | Weak Pull-Up/Pull-Down |
---|---|---|---|---|
SDM_IO0 | Input | 1.8 V LVCMOS | Schmitt Trigger | Weak pull-down with 20 kΩ resistor |
SDM_IO10 | Input | 1.8 V LVCMOS | Schmitt Trigger | Weak pull-up with 20 kΩ resistor |
SDM_IO11 | Input | 1.8 V LVCMOS | Schmitt Trigger | Weak pull-up with 20 kΩ resistor |
SDM_IO12 | Input | 1.8 V LVCMOS | Schmitt Trigger | Weak pull-up with 20 kΩ resistor |
SDM_IO13 | Input | 1.8 V LVCMOS | Schmitt Trigger | Weak pull-up with 20 kΩ resistor |
SDM_IO14 | Input | 1.8 V LVCMOS | Schmitt Trigger | Weak pull-up with 20 kΩ resistor |
SDM_IO16 | Input | 1.8 V LVCMOS | Schmitt Trigger | Weak pull-down with 20 kΩ resistor |
Pin Function | SDM I/O | Direction | I/O Standard | Schmitt Trigger/TTL Input | Weak Pull-Up/Pull-Down | Drive Strength | Open Drain | Slew Rate |
---|---|---|---|---|---|---|---|---|
AVSTx8_DATA2 | SDM_IO1 | Input | 1.8 V LVCMOS | Schmitt Trigger | Disable | — | — | — |
AVSTx8_DATA0 | SDM_IO2 | Input | 1.8 V LVCMOS | Schmitt Trigger | Disable | — | — | — |
AVSTx8_DATA3 | SDM_IO3 | Input | 1.8 V LVCMOS | Schmitt Trigger | Disable | — | — | — |
AVSTx8_DATA1 | SDM_IO4 | Input | 1.8 V LVCMOS | Schmitt Trigger | Disable | — | — | — |
AVSTx8_DATA4 | SDM_IO6 | Input | 1.8 V LVCMOS | Schmitt Trigger | Disable | — | — | — |
AVSTx8_READY | SDM_IO8 | Output | 1.8 V LVCMOS | — | — | 8 mA | Disable | Fast |
AVSTx8_DATA7 | SDM_IO10 | Input | 1.8 V LVCMOS | Schmitt Trigger | Disable | — | — | — |
AVSTx8_VALID | SDM_IO11 | Input | 1.8 V LVCMOS | Schmitt Trigger | Weak pull-down with 20 kΩ resistor | — | — | — |
AVSTx8_DATA5 | SDM_IO13 | Input | 1.8 V LVCMOS | Schmitt Trigger | Disable | — | — | — |
AVSTx8_CLK | SDM_IO14 | Input | 1.8 V LVCMOS | Schmitt Trigger | Disable | — | — | — |
AVSTx8_DATA6 | SDM_IO15 | Input | 1.8 V LVCMOS | Schmitt Trigger | Disable | — | — | — |
SDM I/O | Direction | I/O Standard | Schmitt Trigger/TTL Input | Weak Pull-Up/Pull-Down |
---|---|---|---|---|
SDM_IO0 | Input | 1.8 V LVCMOS | Schmitt Trigger | Weak pull-down with 20 kΩ resistor |
SDM_IO5 | Input | 1.8 V LVCMOS | Schmitt Trigger | Weak pull-up with 20 kΩ resistor |
SDM_IO7 | Input | 1.8 V LVCMOS | Schmitt Trigger | Weak pull-up with 20 kΩ resistor |
SDM_IO9 | Input | 1.8 V LVCMOS | Schmitt Trigger | Weak pull-up with 20 kΩ resistor |
SDM_IO12 | Input | 1.8 V LVCMOS | Schmitt Trigger | Weak pull-up with 20 kΩ resistor |
SDM_IO16 | Input | 1.8 V LVCMOS | Schmitt Trigger | Weak pull-down with 20 kΩ resistor |
Pin Function | Direction | I/O Standard | Drive Strength | Slew Rate |
---|---|---|---|---|
AVST_CLK | Input | 1.2 V LVCMOS |
— | — |
AVST_READY | Output | 1.2 V LVCMOS |
Series 34 Ω OCT without calibration |
Slow |
AVST_VALID | Input | 1.2 V LVCMOS |
— | — |
AVST_DATA | Input | 1.2 V LVCMOS |
— | — |
Pin Function | Direction | I/O Standard | Schmitt Trigger/ TTL Input |
Weak Pull-Up / Pull-Down | Drive Strength | Open Drain | Slew Rate |
---|---|---|---|---|---|---|---|
PWRMGT_SCL | Bidirectional | 1.8V LVCMOS | Schmitt Trigger | Weak pull-up with 20 kΩ resistor | 2 mA | Enable | Slow |
PWRMGT_SDA | Bidirectional | 1.8V LVCMOS | Schmitt Trigger | Weak pull-up with 20 kΩ resistor | 2 mA | Enable | Slow |
PWRMGT_ALERT | Output | 1.8V LVCMOS | — | — | 2 mA | Enable | Slow |
CONF_DONE | Output | 1.8V LVCMOS | — | — | 8 mA | Disable | Fast |
INIT_DONE | Output | 1.8V LVCMOS | — | — | 8 mA | Disable | Fast |
CvP_CONFDONE | Output | 1.8V LVCMOS | — | — | 8 mA | Disable | Fast |
SEU_ERROR | Output | 1.8V LVCMOS | — | — | 8 mA | Disable | Fast |
HPS_COLD_nRESET | Bidirectional | 1.8V LVCMOS | Schmitt Trigger | Weak pull-up with 20 kΩ resistor | 2 mA | Enable | Fast |
Direct to factory image | Input | 1.8V LVCMOS | Schmitt Trigger | Weak pull-down with 20 kΩ resistor | — | — | — |
nCATTRIP | Output | 1.8V LVCMOS | — | — | 2 mA | Disable | Slow |
TAMPERDETECTION | Output | 1.8V LVCMOS | — | — | 8 mA | Disable | Fast |
TAMPERRESPONSESTATUS | Output | 1.8V LVCMOS | — | — | 8 mA | Disable | Fast |