Stratix V Device Handbook: Volume 2: Transceivers

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ID 683779
Date 11/23/2021
Public
Document Table of Contents
Document Table of Contents x
1. Transceiver Architecture in Stratix V Devices 2. Transceiver Clocking in Stratix V Devices 3. Transceiver Reset Control in Stratix V Devices 4. Transceiver Configurations in Stratix V Devices 5. Transceiver Loopback Support in Stratix V Devices 6. Dynamic Reconfiguration in Stratix V Devices
1. Transceiver Architecture in Stratix V Devices x
1.1. Device Layout 1.2. PMA Architecture 1.3. Standard PCS Architecture 1.4. 10G PCS Architecture 1.5. PCIe Gen3 PCS Architecture 1.6. Document Revision History
1.1. Device Layout x
1.1.1. Stratix V GX/GT Channel and PCIe Hard IP Layout 1.1.2. Stratix V GS Channel and PCIe Hard IP Layout
1.1.2. Stratix V GS Channel and PCIe Hard IP Layout x
1.1.2.1. Channel Variants 1.1.2.2. GS/GT/GX Device Variants and Packages
1.2. PMA Architecture x
1.2.1. Receiver Buffer 1.2.2. Receiver Clock Data Recovery Unit 1.2.3. Receiver Deserializer 1.2.4. Transmitter PLLs 1.2.5. Transmitter Serializer 1.2.6. Transmitter Buffer 1.2.7. Transceiver Calibration Blocks 1.2.8. PMA Reconfiguration
1.2.1. Receiver Buffer x
1.2.1.1. Receiver Equalizer Gain Bandwidth 1.2.1.2. Programmable Differential On-Chip Termination (OCT) 1.2.1.3. Programmable VCM 1.2.1.4. Signal Threshold Detection Circuitry 1.2.1.5. DC Gain 1.2.1.6. Continuous Time Linear Equalization (CTLE) 1.2.1.7. Decision Feedback Equalization 1.2.1.8. EyeQ
1.2.1.8. EyeQ x
1.2.1.8.1. Serial Bit Checker
1.2.2. Receiver Clock Data Recovery Unit x
1.2.2.1. Lock-to-Reference Mode 1.2.2.2. Lock-to-Data Mode 1.2.2.3. CDR Lock Modes
1.2.2.3. CDR Lock Modes x
1.2.2.3.1. Automatic Lock Mode 1.2.2.3.2. Manual Lock Mode
1.2.3. Receiver Deserializer x
1.2.3.1. Receiver PMA Bit-Slip
1.2.4. Transmitter PLLs x
1.2.4.1. Channel PLL Used as a CMU PLL (Transmitter PLL) 1.2.4.2. Auxiliary Transmit (ATX) PLL Architecture
1.2.6. Transmitter Buffer x
1.2.6.1. Transmitter Analog Settings 1.2.6.2. Programmable Transmitter On-Chip Termination (OCT) 1.2.6.3. Link Coupling
1.2.7. Transceiver Calibration Blocks x
1.2.7.1. OCT Calibration 1.2.7.2. Offset Cancellation in the Receiver Buffer and Receiver CDR 1.2.7.3. ATX PLL Calibration 1.2.7.4. Calibration Block Boundary
1.3. Standard PCS Architecture x
1.3.1. Receiver Standard PCS Datapath 1.3.2. Transmitter Standard PCS Datapath
1.3.1. Receiver Standard PCS Datapath x
1.3.1.1. Word Aligner 1.3.1.2. PRBS Verifier 1.3.1.3. Deskew FIFO 1.3.1.4. Rate Match (Clock Rate Compensation) FIFO 1.3.1.5. 8B/10B Decoder 1.3.1.6. Byte Deserializer 1.3.1.7. Byte Ordering Block 1.3.1.8. Receiver Phase Compensation FIFO
1.3.1.8. Receiver Phase Compensation FIFO x
1.3.1.8.1. Phase Compensation Mode 1.3.1.8.2. Registered Mode
1.3.2. Transmitter Standard PCS Datapath x
1.3.2.1. Transmitter Phase Compensation FIFO 1.3.2.2. Byte Serializer 1.3.2.3. 8B/10B Encoder 1.3.2.4. PRBS Generator
1.4. 10G PCS Architecture x
1.4.1. Receiver 10G PCS Datapath 1.4.2. Transmitter 10G PCS Datapath
1.4.1. Receiver 10G PCS Datapath x
1.4.1.1. Receiver Gearbox 1.4.1.2. PRBS Verifier 1.4.1.3. Block Synchronizer 1.4.1.4. Disparity Checker 1.4.1.5. Descrambler 1.4.1.6. Frame Synchronizer 1.4.1.7. Bit-Error Rate (BER) Monitor 1.4.1.8. PRP Verifier 1.4.1.9. 64B/66B Decoder 1.4.1.10. CRC-32 Checker 1.4.1.11. Receiver FIFO
1.4.1.2. PRBS Verifier x
1.4.1.2.1. Receiver Inversion
1.4.2. Transmitter 10G PCS Datapath x
1.4.2.1. Transmitter FIFO 1.4.2.2. Frame Generator 1.4.2.3. CRC-32 Generator 1.4.2.4. 64B/66B Encoder 1.4.2.5. Scrambler 1.4.2.6. Disparity Generator 1.4.2.7. PRBS Generator 1.4.2.8. Transmitter Gearbox
1.4.2.5. Scrambler x
1.4.2.5.1. PRP Generator
1.4.2.7. PRBS Generator x
1.4.2.7.1. Transmitter Inversion
1.5. PCIe Gen3 PCS Architecture x
1.5.1. Receiver PCIe Gen3 PCS Datapath 1.5.2. Transmitter PCIe Gen3 PCS Datapath 1.5.3. PIPE Interface
1.5.1. Receiver PCIe Gen3 PCS Datapath x
1.5.1.1. Block Synchronizer 1.5.1.2. Rate Match FIFO 1.5.1.3. Decoder 1.5.1.4. Descrambler 1.5.1.5. Receiver Phase Compensation FIFO
1.5.2. Transmitter PCIe Gen3 PCS Datapath x
1.5.2.1. Transmitter Phase Compensation FIFO 1.5.2.2. Scrambler 1.5.2.3. Encoder 1.5.2.4. Gearbox
1.5.3. PIPE Interface x
1.5.3.1. Auto Speed Negotiation 1.5.3.2. Electrical Idle Inference 1.5.3.3. Clock Data Recovery (CDR) Control
2. Transceiver Clocking in Stratix V Devices x
2.1. Input Reference Clocking 2.2. Internal Clocking 2.3. FPGA Fabric-Transceiver Interface Clocking 2.4. Document Revision History
2.1. Input Reference Clocking x
2.1.1. Input Reference Clock Sources
2.1.1. Input Reference Clock Sources x
2.1.1.1. Dedicated refclk Pins 2.1.1.2. Dedicated refclk Pins Using the Reference Clock Network 2.1.1.3. RX Pins Using the Reference Clock Network 2.1.1.4. Fractional PLLs
2.2. Internal Clocking x
2.2.1. Transmitter Clock Network 2.2.2. Transmitter Clocking 2.2.3. Receiver Clocking
2.2.1. Transmitter Clock Network x
2.2.1.1. Transmitter Clock Lines 2.2.1.2. Clock Dividers 2.2.1.3. Transmitter Clock Network in Stratix V GT Transceiver Channels
2.2.2. Transmitter Clocking x
2.2.2.1. Transmitter 10G PCS Clocking 2.2.2.2. Transmitter Standard PCS Clocking 2.2.2.3. Transmitter GT Channel Clocking
2.2.2.2. Transmitter Standard PCS Clocking x
2.2.2.2.1. Non-Bonded Channel Configurations Using the x1 Clock Network 2.2.2.2.2. Non-Bonded Channel Configurations Using the xN Clock Network 2.2.2.2.3. Bonded Channel Configurations 2.2.2.2.4. Bonded Channel Configurations Using the xN Clock Network 2.2.2.2.5. Bonded Channel Configurations Using the PLL Feedback Compensation Path
2.2.3. Receiver Clocking x
2.2.3.1. GX Channel Receiver Clocking 2.2.3.2. GT Channel Receiver Clocking
2.2.3.1. GX Channel Receiver Clocking x
2.2.3.1.1. Non-Bonded Channel Configurations 2.2.3.1.2. Bonded Channel Configurations
2.3. FPGA Fabric-Transceiver Interface Clocking x
2.3.1. Transmitter Datapath Interface Clocking 2.3.2. Receiver Datapath Interface Clock 2.3.3. GXB 0 PPM Core Clock Assignment
2.3.1. Transmitter Datapath Interface Clocking x
2.3.1.1. Quartus II-Selected Transmitter Datapath Interface Clock 2.3.1.2. Selecting a Transmitter Datapath Interface Clock
2.3.2. Receiver Datapath Interface Clock x
2.3.2.1. Quartus II Software-Selected Receiver Datapath Interface Clock 2.3.2.2. Selecting a Receiver Datapath Interface Clock
3. Transceiver Reset Control in Stratix V Devices x
3.1. PHY IP Embedded Reset Controller 3.2. User-Coded Reset Controller 3.3. Transceiver Reset Using Avalon Memory Map Registers 3.4. Clock Data Recovery in Manual Lock Mode 3.5. Transceiver Blocks Affected by the Reset and Powerdown Signals 3.6. Document Revision History
3.1. PHY IP Embedded Reset Controller x
3.1.1. Embedded Reset Controller Signals 3.1.2. Resetting the Transceiver with the PHY IP Embedded Reset Controller During Device Power-Up 3.1.3. Resetting the Transceiver with the PHY IP Embedded Reset Controller During Device Operation
3.2. User-Coded Reset Controller x
3.2.1. User-Coded Reset Controller Signals 3.2.2. Resetting the Transmitter with the User-Coded Reset Controller During Device Power-Up 3.2.3. Resetting the Transmitter with the User-Coded Reset Controller During Device Operation 3.2.4. Resetting the Receiver with the User-Coded Reset Controller During Device Power-Up Configuration 3.2.5. Resetting the Receiver with the User-Coded Reset Controller During Device Operation
3.3. Transceiver Reset Using Avalon Memory Map Registers x
3.3.1. Transceiver Reset Control Signals Using Avalon Memory Map Registers
3.4. Clock Data Recovery in Manual Lock Mode x
3.4.1. Control Settings for CDR Manual Lock Mode 3.4.2. Resetting the Transceiver in CDR Manual Lock Mode
4. Transceiver Configurations in Stratix V Devices x
4.1. Protocols and Transceiver PHY IP Support 4.2. 10GBASE-R and 10GBASE-KR 4.3. Interlaken 4.4. PCI Express (PCIe)—Gen1, Gen2, and Gen3 4.5. XAUI 4.6. CPRI and OBSAI—Deterministic Latency Protocols 4.7. Transceiver Configurations 4.8. Native PHY IP Configuration 4.9. Stratix V GT Device Configurations 4.10. Document Revision History
4.2. 10GBASE-R and 10GBASE-KR x
4.2.1. 10GBASE-R and 10GBASE-KR Transceiver Datapath Configuration 4.2.2. 10GBASE-R and 10GBASE-KR Supported Features 4.2.3. 1000BASE-X and 1000BASE-KX Transceiver Datapath 4.2.4. 1000BASE-X and 1000BASE-KX Supported Features 4.2.5. Synchronization State Machine Parameters in 1000BASE-X and 1000BASE-KX Configurations 4.2.6. Transceiver Clocking in 10GBASE-R, 10GBASE-KR, 1000BASE-X, and 1000BASE-KX Configurations
4.3. Interlaken x
4.3.1. Transceiver Datapath Configuration 4.3.2. Supported Features 4.3.3. Transceiver Clocking
4.4. PCI Express (PCIe)—Gen1, Gen2, and Gen3 x
4.4.1. Transceiver Datapath Configuration 4.4.2. Supported Features for PCIe Configurations 4.4.3. Supported Features for PCIe Gen3 Block Synchronization (Word Aligner) Gen3 Rate Match FIFO 128B/130B Encoder/Decoder Gen3 Gear Box Scrambler/Descrambler PIPE 3.0-Like Gen3 Interface Auto-Speed Negotiation Block Transmitter Electrical IDLE Generation Receiver Electrical IDLE Inference Gen3 Power State Management CDR Control Block 4.4.4. Transceiver Clocking and Channel Placement Guidelines 4.4.5. Advanced Channel Placement Guidelines for PIPE Configurations 4.4.6. Transceiver Clocking for PCIe Gen3
4.5. XAUI x
4.5.1. Transceiver Datapath in a XAUI Configuration 4.5.2. Supported Features 4.5.3. Transceiver Clocking and Channel Placement Guidelines
4.6. CPRI and OBSAI—Deterministic Latency Protocols x
4.6.1. Transceiver Datapath Configuration 4.6.2. Phase Compensation FIFO in Register Mode 4.6.3. Channel PLL Feedback 4.6.4. CPRI and OBSAI 4.6.5. CPRI Enhancements
4.7. Transceiver Configurations x
4.7.1. Standard PCS Configurations—Custom Datapath 4.7.2. Standard PCS Configurations—Low Latency Datapath 4.7.3. Transceiver Channel Placement Guidelines 4.7.4. 10G PCS Configurations 4.7.5. Merging Instances
4.7.4. 10G PCS Configurations x
4.7.4.1. 10G PCS Datapath Functionality 4.7.4.2. Using the coreclkin Ports
4.8. Native PHY IP Configuration x
4.8.1. Native PHY Transceiver Datapath Configuration 4.8.2. Standard PCS Features 4.8.3. 10G PCS Supported Features 4.8.4. 10G Datapath Configurations with Native PHY IP 4.8.5. PMA Direct Supported Features 4.8.6. Channel and PCS Datapath Dynamic Switching Reconfiguration
4.8.2. Standard PCS Features x
4.8.2.1. Standard PCS Receiver and Transmitter Blocks
4.8.3. 10G PCS Supported Features x
4.8.3.1. 10G PCS Receiver and Transmitter Blocks 4.8.3.2. Receiver and Transmit Gearbox in Native PHY IP
5. Transceiver Loopback Support in Stratix V Devices x
5.1. Serial Loopback 5.2. PIPE Reverse Parallel Loopback 5.3. Reverse Serial Loopback 5.4. Reverse Serial Pre-CDR Loopback 5.5. Document Revision History
6. Dynamic Reconfiguration in Stratix V Devices x
6.1. Dynamic Reconfiguration Features 6.2. Offset Cancellation 6.3. PMA Analog Controls Reconfiguration 6.4. On-Chip Signal Quality Monitoring (Eye Viewer) 6.5. Decision Feedback Equalization 6.6. Adaptive Equalization 6.7. Dynamic Reconfiguration of Loopback Modes 6.8. Transceiver PLL Reconfiguration 6.9. Transceiver Channel Reconfiguration 6.10. Transceiver Interface Reconfiguration 6.11. Document Revision History
1. Transceiver Architecture in Stratix V Devices
2. Transceiver Clocking in Stratix V Devices
3. Transceiver Reset Control in Stratix V Devices
4. Transceiver Configurations in Stratix V Devices
5. Transceiver Loopback Support in Stratix V Devices
6. Dynamic Reconfiguration in Stratix V Devices

4.4.3. Supported Features for PCIe Gen3

The PCIe Gen3 hard PCS supports the Gen3 base specification. PCIe Gen3 operations can be configured using the Stratix V Hard IP for PCI Express IP or PHY IP Core for PCI Express.

In Stratix V Hard IP for PCI Express, selecting PCIe Base Specification Version 3.0 or PCI Express Base Specification Version 2.1 enables a 32-bit wide PIPE 3.0-like interface for Gen1, Gen2, and Gen3 operations.

In PHY IP Core for PCI Express, selecting Gen3 enables the 32-bit wide PIPE 3.0-like interface and selecting Gen1 or Gen2 enables the 16-bit/8-bit wide PIPE 2.0 interface for Gen1 and Gen2 operation.

Block Synchronization (Word Aligner)

The block synchronizer aligns the recovered serial data coming from the CDR to 130-bit word boundaries. The block synchronizer delineates the word boundaries by searching and identifying the Electrical IDLE Exit Sequence Ordered Set (EIEOS) or the Last FTS OS and SKP ordered set to correctly identify the word boundary from the incoming serial data stream. The block synchronizer continues to realign to a new block boundary following the receipt of an SKP ordered set because of varying word lengths.

Gen3 Rate Match FIFO

To accommodate PCIe protocol requirements and to compensate for clock frequency differences of up to ±300 ppm between source and termination equipment, receiver channels have a rate match FIFO. The rate match FIFO adds or deletes four SKP characters (32 bits) to keep the FIFO from becoming empty or full. It monitors the block synchronizer for a skip_found signal. If the rate match FIFO is almost full, the FIFO deletes four SKP characters. If the rate match FIFO is nearly empty, the FIFO inserts an SKP character at the start of the next available SKP ordered set.

128B/130B Encoder/Decoder

Unlike PCIe Gen1 and Gen2, the PCIe Gen3 encoder/decoder does not use 8B/10B encoding. The PCIe Gen3 encoder/decoder uses a 2-bit sync header and a 128-bit data word. The PCS encoder appends the two sync header bits to every 128 bits of data and enables scrambling for the data packets except for ordered set packets and the first symbol of a TS1/TS2 ordered set. The encoder/decoder continuously enables or disables scrambling, based on whether the payload being processed is an ordered set or a data packet. If an Electrical IDLE Exit Ordered Set or a Fast Training Sequence Ordered Set is received, the scrambler is reset to the initial seed value. The encoder/decoder also monitors the data stream for ordered set and sync header bit violations.

Gen3 Gear Box

The PCIe 3.0 base specification requires a block size of 130 bits with the exception of SKP ordered sets, which can be 66, 98, 130, 162, or 194 bits in length. The 130-bit block of data generated by the 128B/130B encoder and variable length SKP characters must be reordered in 32-bit parallel data segments that the PMA serializer can accept. The transceivers employ a gear box to accommodate this fractional bit difference between the 130-bit data word and a fixed 32-bit serialization PMA factor for Gen3.

Scrambler/Descrambler

Scrambling and descrambling are used during PCIe Gen3 operation to guarantee adequate transitions for the receiver in order to correctly regenerate the recovered clock. The 2-bit sync header bit, ordered set, and the first symbol of the TS1/TS2 ordered set are never scrambled.

PIPE 3.0-Like Gen3 Interface

PCIe Gen3 is a new feature added to the transceivers. The PCS supports PCI Express 3.0 base specification. The PIPE interface has been expanded to a 32-bit wide PIPE 3.0-like interface. The PIPE interface controls PHY functions such as transmission of electrical idle, receiver detection, and speed negotiation and control. In summary, the Gen3 PIPE 3.0-like interface block performs the following:

  • Dynamic clock selection between Gen1, Gen2, and Gen3 speeds
  • Gen3 auto speed negotiation (ASN)
  • Controlling the 128B/130B encoder/decoder
  • Gen3 Electrical Idle Entry and Exit detections/CDR Control Block
  • Dynamic Gen3 and Gen2/Gen1 PCS data rate Auto Speed Negotiation
  • Dynamic transceiver PMA data rate and PLL switching

Auto-Speed Negotiation Block

PCIe Gen3 mode enables ASN (auto-speed negotiation) between Gen1 (2.5 Gbps), Gen2 (5.0 Gbps), and Gen3 (8.0 Gbps) signaling data rates. The signaling rate switch is accomplished through frequency scaling and configuration of the PMA and PCS blocks using a fixed 32-bit wide PIPE 3.0-like Interface.

The PMA switches clocks between Gen1, Gen2, and Gen3 data rates in a glitch-free manner. For a non-bonded x1 channel, an ASN module facilitates speed negotiation in that channel. For bonded x2, x4, and x8 channels, the ASN module selects the master channel to control the rate switch. The master channel distributes the speed change request to the other PMA and PCS channels.

Table 36.  PIPE Gen3 32-Bit PCS Clock Rates
PCIe Gen3 Capability Mode Enabled Gen1 Gen2 Gen3
Lane data rate 2.5G 5G 8G
PCS clock frequency 250 MHz 500 MHz 250 MHz
FPGA Core IP clock frequency 62.5 MHz 125 MHz 250 MHz
PIPE interface width 32-bit 32-bit 32-bit
Rate[1:0] 00 01 10

The PCIe Gen3 speed negotiation process is initiated by writing a 1 to bit 5 of the Link Control register of the root port, causing a PIPE rate signal change from the hard IP. The ASN then places the PCS in reset, dynamically shuts down the clock paths to disengage the current active state PCS (either Standard PCS or Gen3 PCS). If a switch to or from Gen3 is requested, the ASN automatically selects the correct PCS clock paths and datapath selection in the multiplexers. The ASN block then sends a request to the PMA block to switch the data rate change and waits for a rate change done signal for confirmation. When the PMA completes the rate change and sends confirmation to the ASN block, ASN enables the clock paths to engage the new PCS block and releases the PCS reset. Successful completion of this process is indicated by assertion of the pipe_phystatus signal by the ASN block to the hard IP block.

Note: In PHY IP Core for PCI Express configuration, the Core IP must set the values to pipe_rate[1:0] to initiate the transceiver datarate switch sequence.
Note: When you switch speeds to either Gen2 or Gen3, hold the LTSSM steady for 700 µs in Recovery.RCVRLOCK. The rx_is_lockedtodata signal from the CDR must be stable during this time. The PHY MAC interface should not look at rxvalid during this time because its contents may be invalid.

Transmitter Electrical IDLE Generation

The PIPE 3.0-like interface under the control of the hard IP block in Hard IP for PCIe or the user Core IP in PHY IP Core for PCIe may place the transmitter in electrical idle during low power states and the ASN process. Before the transmitter enters electrical idle, the HIP sends an electrical idle order set (EIOS) to the PHY. For Gen1 and Gen2, the order set format is COM, IDL, IDL, IDL. For Gen3, the order set format consists of 16 symbols with value 0x66.

During electrical idle, the transmitter differential and common mode voltage levels are compliant to the PCIe Base Specification 3.0.

Receiver Electrical IDLE Inference

If there is no activity on the link for a period of time or during the ASN process, the Inferring Electrical Idle condition is detected by the receiver PHY. These conditions are specified according to Table 4-11 of the PCI Express Base Specification, Rev 3.0.

Gen3 Power State Management

The PCIe base specification defines low power states for PHY layer devices to minimize power consumption. The Gen3 PCS does not implement these power saving measures, except when placing the transmitter driver in electrical idle state in the low power states. In P2 low power state, the transceivers do not disable the PIPE block clock.

CDR Control Block

The CDR control block controls the PMA CDR to obtain bit and symbol alignment and deskew within the allocated time, and generates status signals for other PCS blocks. The PCIe base specification requires that the receiver L0s power state exit time be a maximum of 4 ms for Gen1, 2 ms for Gen2, and 4 ms for Gen3 signaling rates. The transceivers have an improved CDR control block to accommodate fast lock times when the CDR must relock to the new multiplier/divider settings when entering or exiting Gen3 speeds.

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