Visible to Intel only — GUID: nik1409773884180
Ixiasoft
Visible to Intel only — GUID: nik1409773884180
Ixiasoft
2.3.2. Receiver Datapath Interface Clock
- Read side of the RX phase compensation FIFO—for configurations that use the standard PCS channel
- Read side of the RX FIFO—for configurations that use the 10G PCS channel
This interface is clocked by the receiver datapath interface clock. The receiver PCS forwards the following clocks to the FPGA fabric:
- rx_clkout—for each receiver channel in a non-bonded configuration when you do not use a rate matcher
- tx_clkout—for each receiver channel in a non-bonded configuration when you use a rate matcher
- single rx_clkout[0]—for all receiver channels in a bonded configuration
All configurations that use the standard PCS channel must have a 0 ppm difference between the receiver datapath interface clock and the read side clock of the RX phase compensation FIFO.
You can clock the receiver datapath interface by using one of the following:
- Quartus II-selected receiver datapath interface clock
- User-selected receiver datapath interface clock