Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide

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ID 683763
Date 10/02/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. CvP Description 3. CvP Topologies 4. Design Considerations 5. CvP Driver and Registers 6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Agilex™ 7 FPGAs 7. Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide Archives 8. Document Revision History for the Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide
1. Overview x
1.1. Benefits of Using CvP 1.2. CvP System 1.3. CvP Modes
1.3. CvP Modes x
1.3.1. CvP Limitations
1.3.1. CvP Limitations x
1.3.1.1. CvP Error Recovery
2. CvP Description x
2.1. Configuration Images 2.2. CvP Modes 2.3. Compression Features 2.4. Pin Description
2.2. CvP Modes x
2.2.1. CvP Initialization Mode 2.2.2. CvP Update Mode
3. CvP Topologies x
3.1. Single Endpoint 3.2. Multiple Endpoints
4. Design Considerations x
4.1. Designing CvP for an Open System 4.2. Designing CvP for a Closed System
4.1. Designing CvP for an Open System x
4.1.1. FPGA Power Supplies Ramp Time Requirement 4.1.2. PCIe Wake-Up Time Requirement
4.1.2. PCIe Wake-Up Time Requirement x
4.1.2.1. For CvP Initialization Mode 4.1.2.2. For CvP Update Mode
5. CvP Driver and Registers x
5.1. CvP Driver Support 5.2. CvP Driver Flow 5.3. VSEC Registers for CvP
5.3. VSEC Registers for CvP x
5.3.1. Vendor Specific Capability Header Register 5.3.2. Vendor Specific Header Register 5.3.3. Intel® Marker Register 5.3.4. User Configurable Device/Board ID Register 5.3.5. CvP Status Register 5.3.6. CvP Mode Control Register 5.3.7. CvP Data Registers 5.3.8. CvP Programming Control Register 5.3.9. CvP Credit Register
6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Agilex™ 7 FPGAs x
6.1. Implementation of CvP Initialization Mode 6.2. Implementation of CvP Update Mode
6.1. Implementation of CvP Initialization Mode x
6.1.1. Generating the Synthesis HDL files for Supported PCIe* Tile 6.1.2. Setting up the CvP Parameters in Device and Pin Options 6.1.3. Compiling the Design 6.1.4. Converting the SOF File 6.1.5. Bringing up the Hardware
6.1.5. Bringing up the Hardware x
6.1.5.1. Installing the Upstream Open Source CvP Driver in Linux Systems 6.1.5.2. Setting Up the Correct MSEL Switch State 6.1.5.3. Programming CvP Images
6.2. Implementation of CvP Update Mode x
6.2.1. Instantiating the PCIe Hard IP 6.2.2. Setting Up the CvP Parameters 6.2.3. Setting Up the Base Revision 6.2.4. Setting Up and Compile the Updated Revision 6.2.5. Converting the SOF File 6.2.6. Programming the Core RBF file from the Updated Revision via PCIe* Link
6.2.3. Setting Up the Base Revision x
6.2.3.1. Creating a Reserved Core Partition 6.2.3.2. Defining a Logic Lock Region 6.2.3.3. Compiling and Exporting the Root Partition
1. Overview
2. CvP Description
3. CvP Topologies
4. Design Considerations
5. CvP Driver and Registers
6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Agilex™ 7 FPGAs
7. Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide Archives
8. Document Revision History for the Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide

8. Document Revision History for the Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide

Document Version Quartus® Prime Version Changes
2024.10.02 23.1
  • Updated row C in the Power-Up Sequence Timing in CvP Initialization Mode table.
  • Updated the FPGA Power Supplies Ramp-Up Time and POR figure in the FPGA Power Supplies Ramp Time Requirement section.
2024.07.03 23.1 Updated the label in PCIe* Timing Sequence in CvP Initialization Mode figure to FPGA Bottom Left or Top Left Transceiver Status.
2024.04.01 23.1 Added a footnote about delay before configuration in the Setting Up the Correct MSEL Switch State section.
2023.12.04 23.1
  • Updated CvP Modes section as per the following:
    • Updated PCIe* Version details in CvP Support for Agilex™ 7 Device Family table.
    • Updated Bifurcation PCIe* Mode Version details in the table in the note.
    • Updated notes.
  • Updated CvP Initialization Mode section.
  • Updated Pin Description section.
  • Updated PCIe* Timing Sequence in CvP Initialization Mode figure in For CvP Initialization Mode section.
  • Updated Timing Range in Power-Up Sequence Timing in CvP Initialization Mode table in For CvP Initialization Mode section.
  • Added note after Power-Up Sequence Timing in CvP Initialization Mode table in For CvP Initialization Mode section.
  • Updated title for Generating the Synthesis HDL files for Intel FPGA P-Tile Avalon® streaming interface for PCI Express* section to Generating the Synthesis HDL files for Supported PCIe* Tile.
  • Updated steps 5 and 11 in Generating the Synthesis HDL files for Supported PCIe* Tile section.
  • Added additional related information in Generating the Synthesis HDL files for Supported PCIe* Tile section.
  • Updated footnote for the Configuration Scheme in MSEL Pin Settings for Active Serial x4 (Fast mode) Scheme of Agilex™ 7 Devices table in Setting Up the Correct MSEL Switch State section.
2023.08.17 23.1 Updated the recommended QSPI flash size for periphery images in the Configuration Images section.
2023.07.07 23.1
  • Added description on periphery image in Configuration Images section.
  • Added Intel Premier Support ID in Designing CvP for a Closed System section.
2023.04.10 23.1
  • Added PCIe* Version details for R-Tile and F-tile in the CvP Support for Intel Agilex Device Family table.
  • Updated the third note in the CvP Modes section.
  • Updated first bullet point and added a new bullet point in the CvP Limitations section regarding CvP in designs that include the Hard Processor System (HPS).
  • Updated the CvP Update Modesection to include information regarding how performing an FPGA core image update affects the HPS.
  • Updated product family name to " Intel Agilex® 7".
  • Replaced "Avalon-ST" with "Avalon streaming interface".
  • Replaced "Avalon-MM" with "Avalon memory mapped".
2022.12.19 22.4
  • Updated the naming scheme from Gen<X> to PCIe* <X>.0 throughout the document.
  • Updated PCIe* Version details for P-Tile Supported Tile in the CvP Support for Intel Agilex Device Family table.
  • Updated CvP Error Recovery section.
  • Updated Generating the Synthesis HDL files for FPGA P-Tile Avalon Streaming (Avalon-ST) for Express section.
2022.09.26 22.2 Added second note under image in the Implementation of CvP Update Mode section.
2022.08.05 22.2
  • Made changes to the following sections to remove downstream driver support.
    • Updated:
      • CvP Modes
      • CvP Driver Support
      • Installing the Upstream Open Source CvP Driver on Linux Systems
      • Programming CvP Options
      • Programming the Core RBF file from the Updated Revision via PCIe Link
    • Removed:
      • Installing Open Source CvP Driver in Linux Systems
      • Downstream Open Source CvP Driver
  • Added .sof file conditions to CvP Limitations.
  • Updated image and descriptions to reflect six tiles instead of four in CvP System.
2022.05.24 21.4 Removed note about periphery image loading time and configuration from the Power-Up Sequence Timing in CvP Initialization Mode table.
2022.03.02 21.4
  • Updated the CvP System section. The option to enable either lower or upper PCIe Hard block CvP support is enabled in the PCIe Hard IP.
  • Added note for timing sequence i in the Power-Up Sequence Timing in CvP Initialization Mode table.
2021.12.13 21.4 Made the following change:
  • Added conditions used to validate the power-up sequence timing in PCIe* Wake-Up Time Requirement: For CvP Initialization Mode
2021.10.04 21.3 Made the following changes:
  • Revised CvP Support for Agilex™ 7 Device Family table:
    • Added preliminary tag to the R-tile and F-tile content
    • Added note describing the REFCLK_GXP clock behavior in R-tile
  • Added 100ms PCIe* link up time requirement in CvP Initialization Mode.
  • Updated link for Download the OpenSource Linux CvP Downstream Driver in Generating the Synthesis HDL files for Intel® FPGA P-Tile Avalon Streaming (Avalon-ST) for PCIe* Express.
  • Added Implementation of CvP Update Mode section and all related subsections.
2021.07.01 21.2
Sections Updated:
  • CvP Modes [CvP Support for Intel Agilex Device Family Table updated
  • Configuration Images [Periphery image and core image definitions updated]
  • CvP Driver Flow [CvP Driver Flow Flowchart updated]
  • Generating the Synthesis HDL files for FPGA P-Tile Avalon Streaming (Avalon-ST) for Express [Enable CVP information added in Step 7]
  • Setting up the CvP Parameters in Device and Pin Options [Step 2b updated]
  • Downstream open source CvP Driver [This is a new section]
  • Upstream open source CvP Driver [This is a new section]
  • Programming CvP Images [Step 7 and Step 8 updated]
2021.03.24 20.4
Sections Updated:
  • CvP Modes
  • CvP System
2020.12.14 20.4 Removed the SDM_IO15 pin documented in Table: CvP Pin Descriptions and Connection Guidelines.
2020.09.15 19.4
  • Added information about the supported tile in Table: CvP Support for Agilex™ 7 Device Family.
  • Updated following figure and table in section For CvP Initialization Mode:
    • Figure: PCIe Timing Sequence in CvP Initialization Mode
    • Table: Power-Up Sequence Timing in CvP Initialization Mode
2020.01.07 19.4 Initial release.
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