Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide

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ID 683763
Date 10/02/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. CvP Description 3. CvP Topologies 4. Design Considerations 5. CvP Driver and Registers 6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Agilex™ 7 FPGAs 7. Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide Archives 8. Document Revision History for the Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide
1. Overview x
1.1. Benefits of Using CvP 1.2. CvP System 1.3. CvP Modes
1.3. CvP Modes x
CvP Initialization Mode CvP Update Mode 1.3.1. CvP Limitations
1.3.1. CvP Limitations x
1.3.1.1. CvP Error Recovery
2. CvP Description x
2.1. Configuration Images 2.2. CvP Modes 2.3. Compression Features 2.4. Pin Description
2.2. CvP Modes x
2.2.1. CvP Initialization Mode 2.2.2. CvP Update Mode
3. CvP Topologies x
3.1. Single Endpoint 3.2. Multiple Endpoints
4. Design Considerations x
4.1. Designing CvP for an Open System 4.2. Designing CvP for a Closed System
4.1. Designing CvP for an Open System x
4.1.1. FPGA Power Supplies Ramp Time Requirement 4.1.2. PCIe Wake-Up Time Requirement
4.1.2. PCIe Wake-Up Time Requirement x
4.1.2.1. For CvP Initialization Mode 4.1.2.2. For CvP Update Mode
5. CvP Driver and Registers x
5.1. CvP Driver Support 5.2. CvP Driver Flow 5.3. VSEC Registers for CvP
5.3. VSEC Registers for CvP x
5.3.1. Vendor Specific Capability Header Register 5.3.2. Vendor Specific Header Register 5.3.3. Intel® Marker Register 5.3.4. User Configurable Device/Board ID Register 5.3.5. CvP Status Register 5.3.6. CvP Mode Control Register 5.3.7. CvP Data Registers 5.3.8. CvP Programming Control Register 5.3.9. CvP Credit Register
6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Agilex™ 7 FPGAs x
6.1. Implementation of CvP Initialization Mode 6.2. Implementation of CvP Update Mode
6.1. Implementation of CvP Initialization Mode x
6.1.1. Generating the Synthesis HDL files for Supported PCIe* Tile 6.1.2. Setting up the CvP Parameters in Device and Pin Options 6.1.3. Compiling the Design 6.1.4. Converting the SOF File 6.1.5. Bringing up the Hardware
6.1.5. Bringing up the Hardware x
6.1.5.1. Installing the Upstream Open Source CvP Driver in Linux Systems 6.1.5.2. Setting Up the Correct MSEL Switch State 6.1.5.3. Programming CvP Images
6.2. Implementation of CvP Update Mode x
6.2.1. Instantiating the PCIe Hard IP 6.2.2. Setting Up the CvP Parameters 6.2.3. Setting Up the Base Revision 6.2.4. Setting Up and Compile the Updated Revision 6.2.5. Converting the SOF File 6.2.6. Programming the Core RBF file from the Updated Revision via PCIe* Link
6.2.3. Setting Up the Base Revision x
6.2.3.1. Creating a Reserved Core Partition 6.2.3.2. Defining a Logic Lock Region 6.2.3.3. Compiling and Exporting the Root Partition
1. Overview
2. CvP Description
3. CvP Topologies
4. Design Considerations
5. CvP Driver and Registers
6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Agilex™ 7 FPGAs
7. Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide Archives
8. Document Revision History for the Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide

1.3. CvP Modes

The CvP configuration scheme supports the following modes:

  • CvP Initialization mode
  • CvP Update mode

CvP Initialization Mode

This mode configures the CvP PCIe* core using the peripheral image of the FPGA through the on-board configuration device. Subsequently, configures the core fabric and all GPIOs through the PCIe* link.

Benefits of using CvP Initialization mode include:

  • Satisfying the PCIe* wake-up time requirement
  • Saving cost by storing the core image in the host memory

CvP Update Mode

The CvP update mode is available after the FPGA enters user mode. You can configure the device through full chip configuration or CvP initialization initially to bring the device into user mode. In user mode, the PCIe* link is available for normal PCIe* applications as well as to perform an FPGA core image update.

The CvP update mode uses the same process as root partition reuse in block-based design, which allows you to reuse the device periphery.

Choose this mode if you want to update the core image for any of the following reasons:

  • To change or modify core FPGA logic functionality
  • To perform standard updates as part of a release process
  • To customize core processing for different components that are part of a complex system
Table 1.  CvP Support for Agilex™ 7 Device Family
Note: The R-Tile and F-Tile specifications are preliminary, pending the full silicon verification.
Supported Tile PCIe* Version Supported CvP Modes
P-Tile

PCIe* 3.0 x16

PCIe* 4.0 x16

PCIe* 3.0 1x8

PCIe* 4.0 1x8

PCIe* 3.0 2x8

PCIe* 4.0 2x8

CvP Initialization

CvP Update
R-Tile

PCIe* 3.0 1x16

PCIe* 4.0 1x16

PCIe* 5.0 1x16

PCIe* 3.0 2x8

PCIe* 4.0 2x8

PCIe* 5.0 2x8

PCIe* 3.0 1x8 + 2x4

PCIe* 4.0 1x8 + 2x4

PCIe* 5.0 1x8 + 2x4

CvP Initialization

CvP Update
F-Tile

PCIe* 3.0 1x16

PCIe* 4.0 1x16

PCIe* 3.0 1x8

PCIe* 4.0 1x8

PCIe* 3.0 1x4

PCIe* 4.0 1x4

PCIe* 3.0 2x8

PCIe* 4.0 2x8

CvP Initialization

CvP Update
Note: You can only select PCIe* 3.0 and above in PCIe* Hard IP, but the host can down-train the link to PCIe* 1.0 and PCIe* 2.0 if necessary.
Note: Use Port0 and Pin_PERST_0 for CvP when true independent support mode is enabled.
Note: P-Tile: CvP application supported from Quartus® Prime 20.4 onwards.
Note: R-Tile and F-Tile: CvP application supported from Quartus® Prime 21.2 onwards.
Note:

When P-Tile, R-Tile, or F-Tile PCI Express* is used for CvP, it supports bifurcation with the following modes, from Quartus® Prime 22.4 onwards. In this situation, bifurcation is supported on other ports as Port0 is used for CvP.

Supported Tile Bifurcation PCIe* Mode
P-Tile

PCIe* 3.0 2x8

PCIe* 4.0 2x8

R-Tile

PCIe* 3.0 2x8

PCIe* 4.0 2x8

PCIe* 5.0 2x8

PCIe* 3.0 1x8 + 2x4

PCIe* 4.0 1x8 + 2x4

PCIe* 5.0 1x8 + 2x4

F-Tile

PCIe* 3.0 2x8

PCIe* 4.0 2x8

Note: R-Tile: The REFCLK_GXR reference clock to the R-Tile must be on when you want to reconfigure the device.

Section Content
CvP Limitations

Level Two Title