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1. Intel® Stratix® 10 Configuration User Guide
2. Intel® Stratix® 10 Configuration Details
3. Intel® Stratix® 10 Configuration Schemes
4. Including the Reset Release Intel® FPGA IP in Your Design
5. Remote System Update (RSU)
6. Intel® Stratix® 10 Configuration Features
7. Intel® Stratix® 10 Debugging Guide
8. Intel® Stratix® 10 Configuration User Guide Archives
9. Document Revision History for the Intel® Stratix® 10 Configuration User Guide
2.1. Intel® Stratix® 10 Configuration Timing Diagram
2.2. Configuration Flow Diagram
2.3. Device Response to Configuration and Reset Events
2.4. Additional Clock Requirements for HPS, PCIe* , eSRAM, and HBM2
2.5. Intel® Stratix® 10 Configuration Pins
2.6. Configuration Clocks
2.7. Maximum Configuration Time Estimation
2.8. Generating Compressed .sof File
3.1.1. Avalon® -ST Configuration Scheme Hardware Components and File Types
3.1.2. Enabling Avalon-ST Device Configuration
3.1.3. The AVST_READY Signal
3.1.4. RBF Configuration File Format
3.1.5. Avalon-ST Single-Device Configuration
3.1.6. Debugging Guidelines for the Avalon® -ST Configuration Scheme
3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core
3.1.7.4.1. PFL II IP Recommended Design Constraints to FPGA Avalon-ST Pins
3.1.7.4.2. PFL II IP Recommended Design Constraints for Using QSPI Flash
3.1.7.4.3. PFL II IP Recommended Design Constraints for using CFI Flash
3.1.7.4.4. PFL II IP Recommended Constraints for Other Input Pins
3.1.7.4.5. PFL II IP Recommended Constraints for Other Output Pins
3.2.1. AS Configuration Scheme Hardware Components and File Types
3.2.2. AS Single-Device Configuration
3.2.3. AS Using Multiple Serial Flash Devices
3.2.4. AS Configuration Timing Parameters
3.2.5. Maximum Allowable External AS_DATA Pin Skew Delay Guidelines
3.2.6. Programming Serial Flash Devices
3.2.7. Serial Flash Memory Layout
3.2.8. AS_CLK
3.2.9. Active Serial Configuration Software Settings
3.2.10. Intel® Quartus® Prime Programming Steps
3.2.11. Debugging Guidelines for the AS Configuration Scheme
5.1. Remote System Update Functional Description
5.2. Guidelines for Performing Remote System Update Functions for Non-HPS
5.3. Commands and Responses
5.4. Quad SPI Flash Layout
5.5. Generating Remote System Update Image Files Using the Programming File Generator
5.6. Remote System Update from FPGA Core Example
5.6.1. Prerequisites
5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image
5.6.3. Programming Flash Memory with the Initial Remote System Update Image
5.6.4. Reconfiguring the Device with an Application or Factory Image
5.6.5. Adding an Application Image
5.6.6. Removing an Application Image
7.1. Configuration Debugging Checklist
7.2. Intel® Stratix® 10 Configuration Architecture Overview
7.3. Understanding Configuration Status Using quartus_pgm command
7.4. SDM Debug Toolkit Overview
7.5. Configuration Pin Differences from Previous Device Families
7.6. Configuration File Format Differences
7.7. Understanding SEUs
7.8. Reading the Unique 64-Bit CHIP ID
7.9. E-Tile Transceivers May Fail To Configure
7.10. Understanding and Troubleshooting Configuration Pin Behavior
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2.5.2. MSEL Settings
After power-on MSEL[2:0] pins specify the configuration scheme for Intel® Stratix® 10 devices. Use 4.7-kΩ resistors to pull the MSEL[2:0] pins up to VCCIO_SDM or down to ground as required by the MSEL[2:0] setting for your configuration scheme.
Figure 8. MSEL Pull-Up and Pull-Down Circuit Diagram
Configuration Scheme | MSEL[2:0] |
---|---|
Avalon-ST (x32) | 000 |
Avalon-ST (x16) | 101 |
Avalon-ST (x8) | 110 |
AS (Fast mode – for CvP) 5 | 001 |
AS (Normal mode) 6 | 011 |
JTAG only7 | 111 |
You must also specify the configuration scheme on the Configuration page of the Device and Pin Options dialog box in the Intel® Quartus® Prime Software.
Figure 9. Specify Configuration Scheme to Specify MSEL Value
5 If you use AS Fast mode, you must ramp all power supplies to the recommended operating condition within 10 ms. This ramp-up requirement ensures that the AS x4 device is within its operating voltage range when the Intel® Stratix® 10 device begins to access it.
6 If you use AS Normal mode, you must fully ramp the VCCIO_SDM supply to the recommended operating condition within 10 ms.
7 JTAG configuration works with any valid MSEL settings, unless disabled for security.