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1. Intel® Stratix® 10 Configuration User Guide
2. Intel® Stratix® 10 Configuration Details
3. Intel® Stratix® 10 Configuration Schemes
4. Including the Reset Release Intel® FPGA IP in Your Design
5. Remote System Update (RSU)
6. Intel® Stratix® 10 Configuration Features
7. Intel® Stratix® 10 Debugging Guide
8. Intel® Stratix® 10 Configuration User Guide Archives
9. Document Revision History for the Intel® Stratix® 10 Configuration User Guide
2.1. Intel® Stratix® 10 Configuration Timing Diagram
2.2. Configuration Flow Diagram
2.3. Device Response to Configuration and Reset Events
2.4. Additional Clock Requirements for HPS, PCIe* , eSRAM, and HBM2
2.5. Intel® Stratix® 10 Configuration Pins
2.6. Configuration Clocks
2.7. Maximum Configuration Time Estimation
2.8. Generating Compressed .sof File
3.1.1. Avalon® -ST Configuration Scheme Hardware Components and File Types
3.1.2. Enabling Avalon-ST Device Configuration
3.1.3. The AVST_READY Signal
3.1.4. RBF Configuration File Format
3.1.5. Avalon-ST Single-Device Configuration
3.1.6. Debugging Guidelines for the Avalon® -ST Configuration Scheme
3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core
3.1.7.4.1. PFL II IP Recommended Design Constraints to FPGA Avalon-ST Pins
3.1.7.4.2. PFL II IP Recommended Design Constraints for Using QSPI Flash
3.1.7.4.3. PFL II IP Recommended Design Constraints for using CFI Flash
3.1.7.4.4. PFL II IP Recommended Constraints for Other Input Pins
3.1.7.4.5. PFL II IP Recommended Constraints for Other Output Pins
3.2.1. AS Configuration Scheme Hardware Components and File Types
3.2.2. AS Single-Device Configuration
3.2.3. AS Using Multiple Serial Flash Devices
3.2.4. AS Configuration Timing Parameters
3.2.5. Maximum Allowable External AS_DATA Pin Skew Delay Guidelines
3.2.6. Programming Serial Flash Devices
3.2.7. Serial Flash Memory Layout
3.2.8. AS_CLK
3.2.9. Active Serial Configuration Software Settings
3.2.10. Intel® Quartus® Prime Programming Steps
3.2.11. Debugging Guidelines for the AS Configuration Scheme
5.1. Remote System Update Functional Description
5.2. Guidelines for Performing Remote System Update Functions for Non-HPS
5.3. Commands and Responses
5.4. Quad SPI Flash Layout
5.5. Generating Remote System Update Image Files Using the Programming File Generator
5.6. Remote System Update from FPGA Core Example
5.6.1. Prerequisites
5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image
5.6.3. Programming Flash Memory with the Initial Remote System Update Image
5.6.4. Reconfiguring the Device with an Application or Factory Image
5.6.5. Adding an Application Image
5.6.6. Removing an Application Image
7.1. Configuration Debugging Checklist
7.2. Intel® Stratix® 10 Configuration Architecture Overview
7.3. Understanding Configuration Status Using quartus_pgm command
7.4. SDM Debug Toolkit Overview
7.5. Configuration Pin Differences from Previous Device Families
7.6. Configuration File Format Differences
7.7. Understanding SEUs
7.8. Reading the Unique 64-Bit CHIP ID
7.9. E-Tile Transceivers May Fail To Configure
7.10. Understanding and Troubleshooting Configuration Pin Behavior
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5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image
- On the File menu, click Programming File Generator.
- Select Intel® Stratix® 10 from the Device family drop-down list.
- Select the configuration mode from the Configuration mode drop-down list. The current Intel® Quartus® Prime Software only supports remote system update feature in Active Serial x4.
- On the Output Files tab, assign the output directory and file name.
- Select the output file type.
Select the following file types for the Active Serial (AS) x4 configuration mode:
- JTAG Indirect Configuration File (.jic)
- Memory Map File (.map)
- Raw Programming File (.rpd). Generating the .rpd file is optional.
Figure 78. Creating Initial Flash Image - On the Input Files tab, click Add Bitstream, select the factory image .sof file and click Open. Repeat this step for the application image .sof.
- Bitstream_1 is the bitstream for factory image.
- Bitstream_2 is the bitstream for application image.
Figure 79. Input Files Tab: Specifying the .sof - On the Configuration Device tab, click Add Device, select MT25QU02G flash memory and click OK. The Programming File Generator tool automatically populates the flash partitions.
- Select the FACTORY_IMAGE partition and click Edit.
- On the Edit Partition dialog box, select Bitstream_1 as the factory image .sof in the Input file drop-down list. Keep the default settings for the Page and Address Mode. Click OK.
- Select the MT25QU02G flash memory and click Add Partition.
- In the Add Partition dialog box, select Bitstream_2 for the application image .sof in the Input file drop-down list. Assign Page: 1.Keep the default settings for Address Mode. Click OK.
- For Flash loader click Select. Select Intel® Stratix® 10 from Device family list. Select 1SX280LU2 for the Device name. Click OK.
- Click Generate to generate the remote system update programming files. The Programming File Generator generates the following files:
- Initial_RSU_Image.jic
- Initial_RSU_Image_jic.map
Figure 80. Configuration Tab: Add Device, Partition, Flash Loader and Generate
The following example output shows the generated .map file. The .map lists the start addresses of the factory image, CPB0, CPB1, and one application image. The remote system update requires these addresses.
BLOCK START ADDRESS END ADDRESS
BOOT_INFO 0x00000000 0x0010FFFF
FACTORY_IMAGE 0x00110000 0x002D3FFF
SPT0 0x002D4000 0x002DBFFF
SPT1 0x002DC000 0x002E3FFF
CPB0 0x002E4000 0x002EBFFF
CPB1 0x002EC000 0x002F3FFF
Application Image 0x002F4000 0x004B7FFF
Configuration device: 1SX280LU3S2
Configuration mode: Active Serial x4
Notes:
- Data checksum for this conversion is 0xBFFB90A5
- All the addresses in this file are byte addresses
After generating the programming file, you can program the flash memory.