• Updated list of recommended voltage regulators in SDM I/O Pins for Power Management and SmartVID.
• Updated list of third-party flash devices in Understanding Quad SPI Flash Byte-Addressing.
• Added HPS-based serial flash memory layout diagrams in Serial Flash Memory Layout.
• Minor edits and updates in Chapter 5: Remote System Update (RSU) to improve the clarity:
  • Revised Configuration pointer block, Initial RSU image, and factory update image descriptions in the RSU Glossary table.
  • Added a note in Remote System Update Configuration Sequence.
  • Revised RSU_STATUS information in RSU Recovery from Corrupted Images.
  • Revised steps description in Update with the Factory Update Image and Guidelines for Performing Remote System Update Functions for Non-HPS.
  • Revised pointer block description in RSU Image Layout in Flash – SDM Perspective.
  • Revised reliable operation statement in RSU Image Layout – Your Perspective.
  • Added a note in RSU Image Sub-Partitions Layout.
  • Revised the 0x14 offset description in Configuration Pointer Block Layout.
  • Aligned steps across the Generating the Initial RSU Image sub-sections.
  • Aligned steps across the Generating the Application Image sub-sections.

• Added note about AVST_READY in SDM Pin Mapping. AVST_READY is also available in x16 and x32 configuration schemes.
• Updated DATA_ULOCK signal in the Available SDM I/O Pin Assignments for Configuration Signals that Do Not Use Dedicated SDM I/O Pins table. The DATA_ULOCK is only available for Intel® Stratix® 10 GX 10M devices.
• Replaced ISL82XX with LTC3888 device in SDM I/O Pins for Power Management and SmartVID
• Updated MSEL in the MSEL Pull-Up and Pull-Down Circuit Diagram.
• Added Intel® Stratix® 10 GX 10M device in the Maximum Configuration Time Estimation for Intel® Stratix® 10 Devices ( Avalon® -ST) table.
• Added new topic: Generating Compressed .sof File
• Renamed the Compact Flash Memory to the External Non-Volatile Flash Memory in the following figures:
  • Connections for Avalon® -ST x8 Single-Device Configuration
  • Connections for Avalon® -ST x16 Single-Device Configuration
  • Connections for Avalon® -ST x32 Single-Device Configuration
• Updated IP for Use with the Avalon-ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core. Added note about PFL II IP maximum throughput.
• Removed CONF_DONE configuration function from the Required Configuration Signals for the AS Configuration Scheme table.
• Added .rpd programming file in the Output File Types table in the AS Configuration Scheme Hardware Components and File Types.
• Removed QSF Assignment for AS topic.
• Revised JTAG Configuration
• Added guidance about JTAG configuration failure in the Debugging Guidelines for the JTAG Configuration Scheme.
• Added video describing reset importance in the Including the Reset Release Intel® FPGA IP in Your Design.
• Added important note about the RSU SDM Command Use Case in Operation Commands.
• Revised Command List and Description table. Updated description for:
  • CONFIG_STATUS
  • RSU_STATUS
• Added anti-tamper feature to the list of supported security features in Device Security.
• Added Remote System Update tab in the Using the SDM Debug Toolkit. Updated all Intel® Stratix® 10 SDM Debug Toolkit screenshots.

• Added a CvP-related note in the Intel® Stratix® 10 Configuration Overview.
• Revised block diagram descriptions in the Intel® Stratix® 10 Configuration Architecture.
• Revised Secure Device Manager. Added recommendation to use -BK ordering part number suffix for Intel® Stratix® 10 devices with the black key provisioning feature.
• Added new section: Restricting Security Features
• Revised Intel® Stratix® 10 Configuration Timing Diagram.
  • Added a note in the Reconfiguration Timing section.
  • Re-ordered sections for clarity.
• Revised Intel® Stratix® 10 Configuration Flow Diagram section.
  • Renamed Power Up section to Power-On to align the description with the figure.
  • Merged Configuration Start and Configuration Pass sections into the FPGA Configuration section.
  • Renamed Configuration Error section to Failed FPGA Configuration.
  • Minor Re-ordered sections for clarity.
  • Removed JTAG Configuration section. Reposition the existing JTAG configuration note.
  • Moved device response content to a new section: Device Response to Configuration and Reset Events.
• Revised text and figure in SDM I/O Pins for Power Management and SmartVID
• Revised OSC_CLK_1 requirements in OSC_CLK_1 Clock Input
• Added new PFL II IP-related topics:
  • PFL II IP Recommended Constraints for Other Input Pins
  • PFL II IP Recommended Constraints for Other Output Pins
• Revised AS_CLK topic:
  • Updated OS_CLK_1 description in the Supported Configuration Clock Source and AS_CLK Frequencies in Intel® Stratix® 10 Devices table. Added table's description.
  • Added note to clarify configuration behavior for invalid AS_CLK setting.
• Reworded attention note in the Remote System Update Using AS Configuration section.
• Revised the steps for image update in the Updates with the Factory Update Image section.
• Revised Command List and Description table. Updated description for:
  • RSU_STATUS
  • QSPI_OPEN
  • QSPI_SET_CS
  • QSPI_ERASE
• Revised RSU Image Layout in Flash - SDM Perspective. Updated max_retry parameter value description.
• Revised step 2 in the Command Sequence To Perform Quad SPI Operations. The QSPI_SET_CS* command is optional for the AS x4 configuration and mandatory for the JTAG configuration scheme.
• Added new topic: Firmware Version Information
• Clarified usage of Use relative address option in the Application Image Layout and Generating an Application Image sections.
• Revised Updating Decision Firmware. Added statement about updating decision firmware using a combined application image.
• Added a new video guide about debugging SDM-related configuration issues in Intel® Stratix® 10 Debugging Guide.
• Updated the following figures and diagrams:
  • Intel® Stratix® 10 Configuration Interfaces
  • Power-On, Configuration, and Reconfiguration Timing Diagram
  • Recoverable Error during Reconfiguration Timing Diagram
  • Intel® Stratix® 10 FPGA Configuration Flow
  • SDM I/O pins selection in the Specifying Optional Configuration Pins section
  • Configuration Pin Selection in the Intel® Quartus® Prime Pro Edition Software
  • Dual-purpose pins selection in the Enabling Dual-Purpose Pins section
  • Specifying the Slave Device Type for Power Management and VID
  • Specifying the Page Command Setting
  • Configuration clock source selection in the Setting Configuration Clock Source section
  • AS configuration scheme setting in the Active Serial Configuration Software Settings section
• Corrected minor errors and spelling mistakes.

• Globally removed support for 133 MHz and 108 MHz AS_CLK frequencies.
  • Updated the maximum AS_CLK clock rate from 133 MHz to 125 MHz.
  • Updated the maximum AS_CLK data rate from 532 MHz to 500 MHz.
• Updated MSEL Settings topic.
  • Updated footnote for AS Fast mode. To support this mode, all power supplies must ramp-up to the recommended operating condition within 10 ms.
  • Added footnote for AS Normal mode. To support the mode, the V_{CCIO_SDM} supply must ramp-up to the recommended operation condition within 10 ms.
• Revised the Maximum Configuration Time Estimation section. Added hyper initialization description.
• Restructured PFL II IP content in the Avalon® -ST Configuration chapter.
• Added statement in The AVST_READY Signal. The PFL II IP core includes the AVST_READY synchronizer logic if you use PFL II IP core as the configuration host.
• Added note in the PFL II IP Functional Description. The PFL II IP does not support HPS cold reset.
• Added new topics:
  • Designing with the PFL II IP Core for Avalon-ST Single Device Configuration
  • Constraining the PFL II IP Core
  • PFL II IP Recommended Design Constraints to FPGA Avalon-ST Pins
  • PFL II IP Recommended Design Constraints for Using QSPI Flash
  • PFL II IP Recommended Design Constraints for Using CFI Flash
• Added new QSPI flash recommendation for PCIe designs in the AS Configuration Scheme Hardware Components and File Types section.
• Revised footnotes associated with 100 MHz and 125 MHz AS_CLK frequencies in the Supported Configuration Clock Source and AS_CLK Frequencies in Intel® Stratix® 10 Devices table.
• Revised Debugging Guidelines for the AS Configuration Scheme to clarify AS Fast mode ramp-up power supplies requirement of 10 ms.
• Revised statement in the Including the Reset Release Intel FPGA IP in Your Design chapter regarding holding Reset Release Intel FPGA IP in reset after configuration is complete. Removed the INIT_DONE signal dependency.
  • Removed Assigning INIT_DONE To an SDM_IO Pin.
• Revised RSU_IMAGE_UPDATE description in the Command List and Description table.
• Restructured Operation Commands. Removed major and minor error code descriptions for the CONFIG_STATUS and RSU_STATUS commands. The major and minor error codes are now documented as an appendix in the Mailbox Client Intel® FPGA IP User Guide.
• Added important note about updating the decision firmware in the Generating the Initial RSU Image.
• Added new topic: Updating Decision Firmware.
• Added new Use relative address parameter description in the Generating an Application Image section.
  • Updated the Specifying Parameters for an Application .rpd Stored in Flash Memory figure to include the new parameter.
• Revised Understanding Configuration Status Using quartus_pgm command. Added quartus_pgm command for clarity.
• Revised Using the SDM Debug Toolkit.

• Revised CvP description in the Intel® Stratix® 10 Configuration Overview.
• Updated Additional Clock Requirements for HPS, PCIe* , eSRAM, and HBM2 and Configuration Debugging Checklist topics. Added text emphasizes that the clock frequencies must match the frequency setting specified in the Intel® Quartus® Prime software.
• Revised Specifying Boot Order for Intel® Stratix® 10 SoC Devices topic. Added text stating that FPGA reconfiguration is not allowed in the FPGA configuration first mode.
• Revised SDM Pin Mapping topic. Removed text stating that all SDM input signals include Schmitt triggers and all SDM outputs are open collector.
• Revised SDM I/O Pins for Power Management and SmartVID topic. Updated screenshot and list of recommended devices.
• Added clarifying text in the OSC_CLK_1 Clock Input topic. If you use transceivers, you must provide an external clock to the OSC_CLK_1 clock input.
• Added new debugging suggestions in the following topics:
  • Debugging Guidelines for the Avalon® -ST Configuration Scheme
  • Debugging Guidelines for the AS Configuration Scheme
  • Debugging Guidelines for the JTAG Configuration Scheme
• Corrected CFI flash memory device number in Generating and Programing a .pof into SFI Flash. The device number is MT28EW.
• Updated AS Configuration.
  • Added important note about resetting QSPI flash.
  • Added note about MSEL[0] and AS_nCSO0 sharing the same SDM I/O pin.
• Revised Remote System Update Using AS Configuration topic. Removed text regarding the optional usage of Serial Flash Mailbox Client Intel® FPGA IP usage.
• Updated Programming Serial Flash Devices using the AS Interface and Debugging Guidelines for the AS Configuration Scheme with the following text: When you power up the Intel® Stratix® 10 with an empty serial flash device and use the AS interface to program the .rpd file into this serial flash device, you must power cycle the Intel® Stratix® 10 device to configure the device from the flash successfully.
• Revised Intel® Stratix® 10 Remote System Update Configuration Sequence. Added note clarifying the nCONFIG signal status during various use case.
• Updated the Command List and Description table:
  • Corrected response length from 1 to 0 for the QSPI_OPEN, QSPI_CLOSE and QSPI_SET_CS command.
  • Revised RSU_IMAGE_UPDATE command description to include information about resetting QSPI flash and behavior between the external host and FPGA. Removed text: Returns a non-zero response if the device is already processing a configuration command.
  • Revised RSU_IMAGE_UPDATE, QSPI_OPEN, QSPI_WRITE, QSPI_READ_DEVICE_REG, and QSPI_WRITE_DEVICE_REG commands descriptions to include information about resetting QSPI flash.
  • Updated QSPI_SET_CS description. Corrected range HPS can use to access HPS data tonCSO[3:0].
  • Generally updated all commands description.
• Updated error code descriptions in the Error Codes table.
• Added new topic: Error Code Recovery.
• Corrected offset value in Application Image Layout. Offset value is 1F00.
• Added new topic: Generating the Initial RSU Image Using .rbf File.
• Revised step 2 in the Command Sequence To Perform Quad SPI Operations. You must issue the QSPI_SET_CS* command regardless of the configuration scheme.
• Moved nCONFIG, nSTATUS, CONF_DONE and INIT_DONE, and SDM_IO Pins sections from Understanding and Troubleshooting Configuration Pin Behavior to Specifying Optional Configuration Pins.
• Updated nSTATUS topic to clarify nSTATUS during the V_{CCIO_SDM} ramp up.
• Added note in the Sub-Partition Table Layout (SPT Layout) stating that firmware doesn't read the SPT for non-HPS RSU operations.
• Revised CONF_DONE and INIT_DONE topic.
• Corrected minor errors and spelling mistakes.

• Updated QSPI_WRITE and QSPI_READ descriptions in the Command List and Description table. The text specifies that the maximum transfer size is 4 kilobytes or 1024 words.
• Updated note in the Adding an Application Image. The note states: When using HPS to manage RSU, you must update both copies of the Configuration Pointer Block (CPB0 and CPB1) and the sub-partition table (SPT). In a non-HPS case, while updates to both copies of the pointer blocks are mandatory, the updates to the sub-partition table are not required.

• Added Intel® Stratix® 10 GX 10M device limitation in the Secure Device Manager section. The Intel® Stratix® 10 GX 10M device supports authentication, but not advanced security.
• Updated the Additional Clock Requirement for HPS, PCIe, eSRAM, and HBM2 section.
  • Added HPS_OSC_CLK clock in the FPGA Configuration topic.
  • Added new topic: HPS First Configuration.
• Added new video guides for the following sections:
  • Converting .sof to .pof File
  • Generating Programming Files using the Programming File Generator
  • Generating the Initial RSU Image
• Globally corrected the AS_nCSO pin name.
• Globally removed dual-purpose text from the MSEL pin type description. After power on reset, the MSEL pins can be repurposed as chip select pins. However, you cannot reuse the MSEL pins for other purpose.
• Removed anti-tamper description from the OSC_CLK_1 Requirements and Device Security sections. The anti-tamper feature is not available in the Intel® Quartus® Prime software version 20.3.

• Added note on using the Parallel Flash Loader to program multiple QSPI flash device in the IP for Use with the
                 Avalon®
              -ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core: Functional Description section.

• Added new recommendation on clearing the RSU_STATUS command after the JTAG reconfiguration in the Debugging Guidelines for the JTAG Configuration Scheme section.
• Removed outdated text from the Understanding the Reset Release IP Requirement section. The text stated that an Intel® Quartus® Prime Pro Edition legality check prevents you from instantiating more than one instance of the Reset Release Intel FPGA IP.
• Updated the Error Codes table. Added new error code responses:
  • HW_ERROR
  • COMMAND_SPECIFIC_ERROR
• Added Page command support in the SDM I/O Pins for Power Management and SmartVID section.

• Added clarifying note for the Intel® Stratix® 10 GX 10M device support in the Intel® Stratix® 10 Configuration Scheme, Data Width, and MSEL table.
  • Intel® Stratix® 10 GX 10M devices don't support the Avalon® -ST x32, Avalon® -ST x16, AS - fast mode, and AS - normal mode configuration schemes.
• Removed outdated note specific to the MSEL pins from the Avalon® -ST Single-Device Configuration section.
• Removed obsolete AN 891 link in the Including the Reset Release Intel FPGA IP in Your Design section. The specified section already includes the AN 891 content.

• Updated Intel® Stratix® 10 Configuration Overview:
  • Renamed Intel® Stratix® 10 Configuration Data Width, Clock Rates, and Data Rates table to Intel® Stratix® 10 Configuration Scheme, Data Width,and MSEL.
  • Revised CvP section.
  • In the AS Fast Mode section, clarified difference between AS normal mode and AS fast mode.
• Revised configuration bitstream authentication statement in the Secure Device Manager section. During the configuration Start state, the SDM authenticates the the Intel-generated configuration firmware and configuration bitstream, ensuring that configuration bitstream is from a trusted source.
• Added Programmer link in the Updating the SDM Firmware section.
• Updated Intel® Stratix® 10 Configuration Timing Diagram section:
  • Updated the Intel® Stratix® 10 Configuration Timing Diagram figure:
    • Renamed figure from Configuration, Reconfiguration, and Error Timing Diagram to Power On, Configuration, and Reconfiguration Timing Diagram.
    • Aligned Power On Reset line depicted in the figure with the Power On configuration state.
    • Aligned nSTATUS, MSEL[2:0], and AVST_READY signals with the transition between Power On and SDM Start configuration state.
    • Reduced a gap between nCONFIG rising edge and nSTATUS rising edge to emphasize a very small time period.
    • Updated GPIO Status signal during Reconfiguration stage.
    • Removed Configuration Error portion of the timing diagram. Added separate timing diagram for the recoverable and unrecoverable configuration error in the Configuration Error section.
  • Renamed Configuration Error section to Recoverable Configuration Error. Added timing diagram. Revised nCONFIG content.
  • Added new section: Unrecoverable Configuration Error. Added timing diagram for unrecoverable error during the reconfiguration.
  • Revised statement on I/O pins in the POR state in the Power Supply Status section. I/O pins and programming registers remain as don't care if POR doesn't meet the specified time.
• Updated Intel® Stratix® 10 Configuration Flow Diagram:
  • Revised the Intel® Stratix® 10 FPGA Configuration Flow diagram.
  • Revised Power Up section.
  • Added text in the Configuration Start section specifying that the power management activity is ongoing during configuration.
  • In the JTAG Configuration section, added text: If an error occurs during JTAG configuration, the SDM does not assert nSTATUS signal. You can monitor the error messages that the Intel® Quartus® Prime Pro Edition Programmer generates for error reporting.
  • Added new section: Device Response to Configuration and Reset Events.
• Added clarification on E-tile variants in the Additional Clock Requirements for HPS, PCIe* , eSRAM, and HBM2 section. Replaced E-tile variants with E-tile transceiver reference clocks.
• Updated figure in the Specifying Optional Configuration Pins section.
• Updated OSC_CLK_1 Clock Input:
  • Added text: When you specify OSC_CLK_1 for configuration, the OSC_CLK_1 clock must be a stable and free-running clock..
  • Removed .qsf file example. Use the Intel® Quartus® Prime Pro Edition GUI to specify frequencies.
  • Expanded topic to include additional usage requirements.
• Added new topic: Maximum Configuration Time Estimation.
• Removed the following sections from the Avalon® -ST Configuration scheme:
  • QSF Assignment for Avalon® -ST x8
  • QSF Assignment for Avalon® -ST x16
  • QSF Assignment for Avalon® -ST x32
• Updated AS Configuration section:
  • Revised Required Configuration Signals for the AS Configuration Scheme table. Removed outdated table description.
  • Revised AS_nCSO statement in the MSEL Pin Function for the AS x4 Configuration Scheme section.
  • Corrected OSC_CLK_1 frequency from 80 MHz to 71.5 MHz in the Maximum AS_CLK Frequency as a Function of Board Capacitance Loading and Clock Source and the Supported Configuration Clock Source and AS_CLK Frequencies in Intel® Stratix® 10 Devices table.
  • Added new table: T_{ext_delay} as a Function of AS_CLK Frequency in the AS Configuration Timing Parameters section.
  • Added notes in the Supported configuration clock source and AS_CLK Frequencies in Intel® Stratix® 10 Devices table clarifying that you observe a lower AS_CLK frequency when accessing the flash during user mode.
  • Revised step describing the programming file(s) generation in the Generating Programming Files using the Programming File Generator. Added command to save the programming file.
• Removed guidelines related to SD/MMC device configuration in the following sections:
  • Removed SD/MMC flash memories support in the Intel® Stratix® 10 Configuration Overview section.
  • Removed SD/MMC configuration scheme from the Intel® Stratix® 10 Configuration Data Width, Clock Rates, and Data Rates table.
  • Removed SD/MMC interface from the Intel® Stratix® 10 Configuration Interfaces figure.
  • Removed SD/MMC block from the SDM Block Diagram figure and the corresponding description.
  • Removed SD/MMC x4/x8 configuration scheme from the MSEL Settings for Each Configuration Scheme of Intel® Stratix® 10 Devices table.
  • Removed SD/MMC text from the CLIENT_ID_NO_MATCH description in the Error Codes table.
• Updated the JTAG Configuration section to include .rbf file as supported option to configure FPGA using the Intel® Quartus® Prime Programmer.
• Updated recommendations on how to debug the OSC_CLK_1 clock based configuration in the Debugging Guidelines for the AS Configuration Scheme topic.
• Removed UNKNOWN_BR error from the Error Codes table.
• Removed PUF data from flash memory section and figures. For more information, refer to the Intel Stratix 10 Device Security User Guide.
• Revised step on selecting factory and application images in the Generating the Initial RSU Image and the Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image sections.
• Revised flash offset for factory image, sub-partition tables, pointer blocks, and application images in the Flash Sub-Partitions Layout table.
• Added guidance on increasing the reserved memory space for factory and application images in the RSU Sub-Partitions Layout section. Revised flash offsets in the Flash Sub-Partitions Layout table.
• Revised System and Read only flag description in the Flags Specifying Contents and Access table.
• Added note and offset for the first image pointer slot in the Pointer Block Layout table. The offset is 0x20.
• Revised item 2 in the General Configuration Debugging Checklist table. Added PWRMGT_SDA and PWRMGT_SCL resistors.
• Added new topic: Understanding Configuration Status using quartus_pgm Command.
• Updated SDM Debug Toolkit:
  • Added temperature sensor image in the Temperature Sensor section.
  • Added new QSPI Flash section.
• Corrected minor errors and spelling mistakes.

• Added PUF data to figures illustrating the layout of flash memory.
• Added the following additional case to the to the reasons that configuration using the OSC_CLK_1 pin might fail: You have enabled the Anti-tamper response security setting on the Assignments > Device > Device and Pin Options > Security > Anti-Tamper tab. The anti-tamper functionality requires you to use the internal oscillator for configuration.
• Added notes in the Generating an Application Image and Generating a Factory Update Image topics, that the rsu1.tcl script turns on bit swap when generating the .rpd file. Consequently, if you are using rsu1.tcl, you should leave bit swap off when generating the .rpd file.
• Removed the following statement from the Application Image Layout topic: By default the first 16 bytes of the application image starting at address offset 0x1FC0 are 0. However you can use these 16 bytes to store a Version ID to identify your application image. This feature is not supported.
• Corrected minor errors and spelling mistakes.

• Corrected the output IBIS model in the Intel® Stratix® 10 Configuration Pins I/O Standard, Drive Strength, and IBIS Model table. The output IBIS model is 18_io_d8s1_sdm_lv.

• Added a new chapter covering the Reset Release Intel® FPGA IP and why it must be included in your design.
• Added the following components to the Required Communication and Host Components for the Remote System Update Design Example figure:
  • Reset Release Intel® FPGA IP
  • 3 Reset Bridge Intel® FPGA IPs
• Added the following text to the OSC_CLK_1 Clock Input topic: When you specify OSC_CLK_1 for configuration and reconfigure without powering down the Intel® Stratix® 10 device, the device can only reconfigure with OSC_CLK_1. In this scenario, OSC_CLK_1 must be a free-running clock.
• Added the following text to the definition of the Failing image field of the RSU_STATUS command:
  Note: A rising edge on nCONFIG to reconfigure from ASx4, does not clear this field. Information about failing image only updates when the Mailbox Client receives a new RSU_IMAGE_UPDATE command and successfully configures from the update image.
• Added the following restriction to the definition of QSPI_SET_CS: Access to the QSPI flash memory devices using SDM_IO pins is only available for the AS x4 configuration scheme, JTAG configuration, and a design compiled for ASx4 configuration. For the Avalon® ST configuration scheme, you must connect QSPI flash memories to GPIO pins.
• Updated the final suggestion in Debugging Guidelines for the JTAG Configuration Scheme topic, to the following: When the MSEL setting on the PCB is not JTAG, if you use the JTAG interface for reconfiguration after an initial reconfiguration using AS or the Avalon® -ST interface, the .sof must be in the file format you specified in the Intel® Quartus® Prime project. For example, if you initially configure the MSEL pins for AS configuration and configure using the AS scheme, a subsequent JTAG reconfiguration using a .sof generated for Avalon® -ST fails.
• Annotated the figures illustrating RSU in the Remote System Update from FPGA Core Example chapter.

• Corrected definition of RSU_STATUS command. This command has 9, not 10 words.
• Added E-Tile Transceivers May Fail To Configure to the Debugging chapter.
• Revised the Modifying the List of Application Images topic.

• Added the an eighth word to the to the RSU_STATUS response: Word 8: Current image retry counter.
• Added new field to the 5th word of the RSU_STATUS response. This field specifies the source of a reported error.
• Added RSU_NOTIFY to the available operation commands.
• Changed the number of images that the Programming File Generator supports from 3 to 7.
• Corrected the definition of word 2 of the RSU_STATUS response. A value of all 0s indicates no failing image.
• Removed write restrictions for lower addresses in flash memory. (The device firmware must still reside at address 0x0.
• Changed the err status pulse range from 1 ms ±50% to 0.5 ms to 10 ms.
• Removed the SDM Firmware state from the Intel® Stratix® 10 FPGA Configuration Flow diagram. This state is part of the FPGA Configuration state.
• Added statement that when using using the Generic Serial Flash Interface Intel® FPGA IP to write the flash memory the flash device must be connected to GPIO pins.
• Updated recommendations on how to debug a corrupt configuration bitstream for the AS x4 configuration scheme in the Debugging Guidelines for the AS Configuration Scheme topic.
• Updated figures that show optional SDM I/O pin assignments. There are additional optional SDM I/O pins in 19.3
• Renamed the following components:;
  • Reset Release Intel® Stratix® 10 FPGA IP to Reset Release Intel® FPGA IP
  • Mailbox Client Intel® Stratix® 10 FPGA IP to Mailbox Client Intel® FPGA IP
  • Intel® Stratix® 10 Serial Flash Mailbox Client Intel® FPGA IP to Serial Flash Mailbox Client Intel® FPGA IP
  • Partial Reconfiguration External Configuration Controller Intel® Stratix® 10 FPGA IP to Partial Reconfiguration External Configuration Controller Intel® FPGA IP
  • Corrected the signal name in The AVST_READY Signal topic: The device can starting sending data when AVST_READY asserts.
  • Added note that the Avalon® ST x32 configuration scheme is limited to 3, DDR x72 DDR external memory interfaces. The Avalon® ST x8 and x16 configuration schemes can support up to 4, x72 DDR external memory interfaces.
• Corrected minor errors and typos.

• Corrected numbers on Configuration, Reconfiguration, and Error Timing Diagram timing diagram. The number 3 now labels the nCONFIG rising edge. Renumbered associated text under the Initial Configuration Timing heading.
• In the Additional Clock Requirements for HPS, PCIe* , eSRAM, and HBM2 topic, removed the following items from the list of components requiring a free-running clock before configuration begins:
  • EMIF
  • E-Tile transceiver
  Note: HPS EMIF retains this requirement.

• Revised and reorganized all topics covering configuration pin assignments:
  • Clarified the behavior of the MSEL pins in AS x4 mode.
  • Added information about the SDM_IO pin states during power-on and after device cleaning to the Intel® Stratix® 10 Configuration Pins topic.
  • Created separate topics covering partial configuration and SmartVID signals.
• Made the following changes to the RSU chapter:
  • Added the following topics:
    • RSU Glossary
    • Standard (non-RSU) Flash Layout
    • RSU Flash Layout – SDM Perspective
    • RSU Flash Layout – Your Perspective
    • Detailed Quad SPI Flash Layout
    • Sub-partitions Layout
    • Sub-Partition Table Layout
    • Pointer Block Layout
    • Modifying the List of Application Images
    • Application Image Layout
  • The static firmware has been replaced by decision firmware.
  • The update image now includes the factory image, the decision firmware and the decision firmware data.
  • The QSPI_ERASE command is now 4 KB aligned. The number of words to erase must be a multiple of 1024.
  • Added definitions of major and minor error codes for RSU_STATUS and CONFIG_STATUS.
• Added footnote explaining that before you can use CvP you must configure either the periphery image or the full image via the AS configuration scheme. Then, you can configure the core image using CvP.
• Added recommendation to use the Analog Devices LTM4677 device to regulate the PMBus for SmartVID devices. You set this parameter here: Device > Device and Pin Options > Power Management & VID > Slave device type.
• Added two restrictions to the dual-purpose use of Avalon® -ST pins. For more information, refer to the Enabling Dual-Purpose Pins topic.
• Corrected maximum speed and data rate in the Intel® Stratix® 10 Configuration Data Width, Clock Rates, and Data Rates table. The Max Clock Rate is 33 MHz. The Max Data Rate is 33 Mb.
• Updated the Intel® Stratix® 10 Reset Release IP to include reference to the new An 891: Using the Reset Release FPGA IP. Removed recommendation to gate Intel® Hyperflex™ registers using the nINIT_DONE signal.
• Added the eSRAM clocks to the list of free-running clocks that must be stable before configuration begins.
• Added Attention warning that designs including the Intel® Stratix® 10 Mailbox Client FPGA IP using Intel® Quartus® Prime Programmer 19.2 or later whose .sof was generated in Intel® Quartus® Prime Programmer 19.1 or earlier must be regenerate the .sof.
• Added 10 kΩ pull-up resistor to nCONFIG in the following figures:
  • Connections for Avalon® -ST x8 Single-Device Configuration
  • Connections for Avalon® -ST x16 Single-Device Configuration
  • Connections for Avalon® -ST x32 Single-Device Configuration
  • PFL II IP core with Dual CFI Flash Memory Devices
• Removed discrete synchronizers for the AVST_READY signal in the following figures:
  • Connections for Avalon® -ST x8 Single-Device Configuration
  • Connections for Avalon® -ST x16 Single-Device Configuration
  • Connections for Avalon® -ST x32 Single-Device Configuration
  If necessary, you can implement synchronizers in the host controller if the host is an FPGA or CPLD. Validation has shown that external synchronizers are not required.
• Made a global change recommending that you use the newer Intel® Quartus® Prime Programming File Generator instead of the legacy Intel® Quartus® Prime Convert Programming Files conversion program to generate programming files. Changed all file conversion topics to use the Programming File Generator.
• Revised all topics providing steps for file conversion to use Programming File Generator instead of the legacy Convert Programming Files dialog box.
• Clarified statement on quad SPI flash byte addressing: The SDM configures the Quad SPI flash device to operate using 4-byte addressing if the flash size in 256 MB or greater.
• Corrected flash memory sizes in Understanding Quad SPI Flash Byte-Addressing topic. All sizes in in megabits or gigabits, not megabytes or gigabytes.
• Generalized Figure 2. Intel® Stratix® 10 Configuration Architecture Block Diagram. This figure no longer lists specific variants of Intel® Stratix® 10 device.
• Corrected Step 3 in the Initial Configuration Timing description. The step should say, with nConfig low, the SDM enters Idle mode after booting.
• Corrected the Intel® Stratix® 10 FPGA Configuration Flow diagram. The transition between FPGA Config* and User Mode should say INIT_DONE = HIGH.
• Corrected the following statement in the Debugging Guidelines for the JTAG Configuration Scheme topic: An nSTATUS falling edge terminates any JTAG access and the device reverts to the MSEL-specified boot source. nSTATUS must be stable during JTAG configuration.. In both sentence, nSTATUS should be nCONFIG.
• Removed pin assignments for CVP_CONFDONE for the Avalon® -ST in the Available SDM I/O Pin Assignments for Configuration Signals that Do Not Use Dedicated SDM I/O Pins table. CvP does not the support Avalon® -ST x8 configuration scheme in Intel® Stratix® 10 devices.

• Added Intel® Stratix® 10 Reset Release IP. Use the nINIT_DONE output of this IP to hold your application logic in reset until the entire FPGA fabric enters user mode.
• Added Configuration Scheme Components and File Types topics illustrating the software flow and programming file outputs for the AS, Avalon® -ST, and JTAG programming schemes.
• Added the following topics to the Stratix 10 Configuration Debugging Guide chapter:
  • Debugging Checklist
  • SDM Debug Toolkit Overview
  • Using the SDM Debug Toolkit
  • Reading the Unique 64-Bit CHIP ID
  • Understanding SEUs
• Added Maximum Allowable External AS_DATA Pin Skew Delay Guidelines topic.
• Added Generating an Update Image for Static Firmware and Factory Image topic.
• Added topics covering SDM_IO pin assignments and QSF settings for the Avalon® -ST x8, x16, x32, and AS configuration schemes.
• Added note in the Avalon® -ST Configuration Timing topic. This note covers special requirements for driving configuration data Avalon® -ST x16 and x32 configurations.
• Added the following signals to the Intel® Stratix® 10 Configuration Timing Diagram: nINIT_DONE, Data<n>-1:0], AVST_READY, AVST_VALID, and AS_CS0.
• Added a 10K Ω pull-up resistor to nCONFIG and corrected file type for flash image in the following figures:
  • Connections for AS x4 Single-Device Configuration
  • Connections for AS Configuration with Multiple Serial Flash Devices
  • Connections for Programming the Serial Flash Devices using the JTAG Interface
• Added the IBIS model name to the Intel® Stratix® 10 Configuration Pins I/O Standard and Drive Strength table. Renamed this table Configuration Pins I/O Standard, Drive Strength, and IBIS Model.
• Added Updating the SDM Firmware topic in the Intel® Stratix® 10 Configuration Overview chapter.
• Added the following guidance in Debugging Guidelines for the JTAG Configuration Scheme topic: When you use the JTAG interface for reconfiguration after an initial reconfiguration using AS or the Avalon® -ST interface, the .sof must be in the file format you specified in the Intel® Quartus® Prime project.
• Added the following signals to the list of device configuration pins that do not have fixed assignments:
  • CONF_DONE
  • INIT_DONE
  • HPS_COLD_nRESET
• Improved definitions of programming file output types.
• Edited Using the PFL II IP Core for clarity and style. Added many screenshots illustrating the step to complete a task.
• Updated the supported flash memory devices and supported SD* card types in the Intel® Stratix® 10 Configuration Overview topic.
• Updated the SDM Pin Mapping table to include the following:
  • Avalon® -ST x16, and x32 configuration scheme
  • Pins for SmartVID
• Added definition of the GETDESIGN_HASH command to the Mailbox Client Intel® Stratix® 10 FPGA IP Command List and Description table.
• Renamed the topic title Commands and Error Codes to Commands and Responses.
• Updated the descriptions for Length and Command Code/Error Code in the Mailbox Client Intel® Stratix® 10 FPGA IP Command and Response Header Description table.
• Added PLL reference clock requirement to the Additional Clock Requirements for Transceivers, HPS, PCIe* , High Bandwidth Memory (HBM2) and SmartVID topic.
• Updated the Generating a Single RSU Image topic to clarify that the .rpd for Intel® Stratix® 10 devices now includes firmware pointer information for image addresses and is not compatible with earlier generation methods.
• Removed a note in Remote System Upgrade Configuration Images topic, saying that the application image is optional and can be added later. The initial RSU setup requires both a factory image and an application image.
• Added the following note to the Configuration Firmware Pointer Block (CPB) topic:
  Note: Application images must align to partition boundaries in the flash device. If an application image is less than a full partition, the rest of the sector cannot be used.
• Added a new topic RSU Recovery from Corrupted Images that explains how the SDM recovers from attempts to load corrupted images.
• Added 71.5 MHz as a supported frequency for the OSC_CLK_1 for AS configuration.
• Added description of optional 16-byte .rpd Version ID to the Remote System Upgrade Flash Device Layout topic.
• Removed Supported Flash Devices appendix. This appendix has been replace by the following web page Supported Flash Devices for Intel® Stratix® 10 Devices which provides more information about flash devices for different purposes.
• Removed references to P30 and P33 flash memory devices. These CFI flash devices are no longer available.

Made the following corrections:

• Corrected the following statement: Because Intel® Stratix® 10 devices operate at 1.8 volt and all SD MMC I/Os operate between 2.7 - 3.6 volts, an intermediate voltage level translator is necessary for SD* cards. This statement is only true for SD* cards.
• Corrected the value of MSEL for Avalon® -ST x16 configuration in Table 1 and Table 9. The correct value is 101.
• Corrected PFL II IP core with Dual P30 or P33 CFI Flash Memory Devices figure. The nCONFIG signal should not have a pulldown resistor.
• Removed the statement that Remote system upgrade cannot use partial reconfiguration (PR) images for the application image from the Remote System Upgrade Using AS Configuration topic. Remote system upgrade does support PR.
• In the Mailbox Client Intel® Stratix® 10FPGA IP Command List and Description table, for CONFIG_STATUS, corrected the size of MSEL. MSEL is 3 bits.
• Corrected the end address in step 14a of Generating a Standard RSU Image. It should be 0x00523FF.
• Corrected the definition of QSPI_ERASE. The number of words to erase must be a multiple of 4000 (hexadecimal) words.
• Changed Number of Commands and Number of Responses to Command Length and Response Length in the Mailbox Client Intel® Stratix® 10 FPGA IP Command List and Descriptions (RSU Functions for Non-HPS Variants) table.
• Corrected the fields of the RSU_STATUS command. The Last failing image field should be called the First failing image. This field reports the flash offset of the first failing application image.
• In the Remote System Upgrade Flash Memory Layout table, changed the amount of reserved flash memory image from 64k to 256k.

• Changed the number of remote system upgrade images supported from more than 500 to 507 in Remote System Upgrade Configuration Images.
• Updated the last two entries in the Configuration Firmware Pointer Block Format table.

• Corrected statement in the Remote System Upgrade topic. A command to the Mailbox Client Intel® Stratix® 10 FPGA Mailbox Client IP Core initiates reconfiguration.
• Corrected the Intel Stratix 10 Remote System Upgrade Components figure and Related Information link. The mailbox component is the Mailbox Client Intel® Stratix® 10 FPGA IP Core.

• Added new chapter, Remote System Upgrade
• Added new chapter, Intel® Stratix® 10 Debugging Guide
• Added separate Debugging Guidelines topics in the Avalon® -ST, AS, and JTAG configuration scheme sections.
• Significantly expanded Stratix 10 Configuration Overview Configuration Overview chapter.
• Added Additional Clock and SmartVID Requirements for Transceivers, HPS, PCIe* , High Bandwidth Memory (HBM2) and SmartVID topic.
• Expanded OSC_CLK_1 Clock Input topic to include additional usage requirements.
• Added AS Using Multiple Serial Flash Devices topic.
• Added numerous screenshots illustrating Intel® Quartus® Prime Pro Edition procedures.
• Improved many figures illustrating configuration schemes.
• Added the fact that you must have system administrator privileges to define a new flash device in the Defining New CFI Flash Memory Device topic.
• Added MT28EW to the list of PFL II flash devices supported.
• Moved almost all of the material describing the PFL II flash from an appendix to the Intel® Stratix® 10 Configuration Schemes chapter.
• Edited entire document for clarity and style.
• Corrected minor errors and typos.

• Removed Estimating the .qek Active Serial Configuration Time section.
• Updated the OSC_CLK_1 supported frequency.
• Added selecting flash loader step to Generating Programming Files using Convert Programming Files.
• Added a note to TCK, TDI, TMS, and TDO stating that they are available for HPS JTAG chaining in SoC devices.
• Removed instruction to drive nCONFIG low from POR in the following diagrams:
  • Connections for AS x4 Single-Device Configuration
  • Connection Setup for AS Configuration with Multiple EPCQ-L Devices
  • Connection Setup for Programming the EPCQ-L Devices using the JTAG Interface
• Added a note in OSC_CLK_1 Clock Input stating that reference clocks to EMIF and PCIe IP cores must be stable and free running.
• Removed .ekp file from Overview of Intel® Quartus® Prime Supported Files and Tools for Configuration and Programming figure.
• Updated the Configuring Intel® Stratix® 10 Devices using AS Configuration section title to Generating and Programming AS Configuration Programming Files.
• Updated Configuration Schemes and Features Overview in Intel Stratix 10 Devices table:
  • Added a note stating to contact sales representative for more information about support readiness.
  • Added a note stating to contact sales representative for more information about flash support other than EPCQ-L devices.
• Removed NAND configuration support.
• Updated Configuration Sequence in Intel Stratix 10 Devices figure by adding a looped flow arrow during Idle state.
• Updated the MSEL note in Intel Stratix 10 Device Configuration Pins table.
• Added a note to recommend OSC_CLK_1 for configuration clock source in OSC_CLK_1 Clock Input.
• Updated CvP data width and maximum data rate in Configuration Schemes and Features Overview in Intel® Stratix® 10 Devices table.
• Removed the multiple EPCQ-L configuration device support.