AN 757: 1G/2.5G Ethernet Design Examples

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ID 683753
Date 11/12/2018
Public
Document Table of Contents
Document Table of Contents x
AN 757: 1G/2.5G Ethernet Design Examples
AN 757: 1G/2.5G Ethernet Design Examples x
Features Hardware and Software Requirements Functional Description Using the Design Example Simulation Hardware Testing Interface Signals Configuration Registers Document Revision History for AN 757: 1G/2.5G Ethernet Design Examples
Functional Description x
Design Components Reset Scheme Clocking Scheme
Simulation x
Testbench Using the Simulator Test Case—Design Example without the IEEE 1588v2 Feature
Hardware Testing x
Setup Test Procedure
Interface Signals x
Clock and Reset Interface Signals Avalon-MM Interface Signals Avalon-ST Interface Signals PHY Interface Signals IEEE 1588v2 Timestamp Interface Signals Packet Classifier Interface Signals TOD Interface Signals
Configuration Registers x
Transceiver Reconfiguration
AN 757: 1G/2.5G Ethernet Design Examples

Using the Design Example

To start using the design example, follow these steps:
  1. Unzip the design files in the project directory.

    tar -zxvf LL_Ethernet_1G_2p5G_A5.tar.gz

  2. Change directory to the following directory:
    • LL10G_A5_1G_2_5G for the design example without the IEEE 1588v2 feature, or
    • LL10G_A5_1G_2_5G_1588v2 for the design example with the IEEE 1588v2 feature.
  3. Launch the Intel® Quartus® Prime software and open the project file, altera_eth_top.qpf.
  4. Select Processing > Start Compilation to compile the design example.
Related Information
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