AN 757: 1G/2.5G Ethernet Design Examples

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ID 683753
Date 11/12/2018
Public
Document Table of Contents
Document Table of Contents x
AN 757: 1G/2.5G Ethernet Design Examples
AN 757: 1G/2.5G Ethernet Design Examples x
Features Hardware and Software Requirements Functional Description Using the Design Example Simulation Hardware Testing Interface Signals Configuration Registers Document Revision History for AN 757: 1G/2.5G Ethernet Design Examples
Functional Description x
Design Components Reset Scheme Clocking Scheme
Simulation x
Testbench Using the Simulator Test Case—Design Example without the IEEE 1588v2 Feature
Hardware Testing x
Setup Test Procedure
Interface Signals x
Clock and Reset Interface Signals Avalon-MM Interface Signals Avalon-ST Interface Signals PHY Interface Signals IEEE 1588v2 Timestamp Interface Signals Packet Classifier Interface Signals TOD Interface Signals
Configuration Registers x
Transceiver Reconfiguration
AN 757: 1G/2.5G Ethernet Design Examples

Testbench

Figure 7. Block Diagram of the Testbench
Table 2.  Testbench Components
Component Description
Device under test (DUT) The design example.
Avalon driver Consists of Avalon-ST master bus functional models (BFMs). This driver forms the TX and RX paths. The driver also provides access the Avalon-MM interface of the DUT.
Ethernet packet monitors Monitor TX and RX datapaths, and display the frames in the simulator console.
Level Two Title