AN 757: 1G/2.5G Ethernet Design Examples

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ID 683753
Date 11/12/2018
Public
Document Table of Contents
Document Table of Contents x
AN 757: 1G/2.5G Ethernet Design Examples
AN 757: 1G/2.5G Ethernet Design Examples x
Features Hardware and Software Requirements Functional Description Using the Design Example Simulation Hardware Testing Interface Signals Configuration Registers Document Revision History for AN 757: 1G/2.5G Ethernet Design Examples
Functional Description x
Design Components Reset Scheme Clocking Scheme
Simulation x
Testbench Using the Simulator Test Case—Design Example without the IEEE 1588v2 Feature
Hardware Testing x
Setup Test Procedure
Interface Signals x
Clock and Reset Interface Signals Avalon-MM Interface Signals Avalon-ST Interface Signals PHY Interface Signals IEEE 1588v2 Timestamp Interface Signals Packet Classifier Interface Signals TOD Interface Signals
Configuration Registers x
Transceiver Reconfiguration
AN 757: 1G/2.5G Ethernet Design Examples

Design Components

Table 1.  Design Components
Component Description
LL 10GbE MAC

The Low Latency Ethernet 10G MAC Intel® FPGA IP with the following configuration:

  • Speed: 1G/2.5G
  • Datapath options: TX & RX
  • Enable ECC on memory blocks: Not selected
  • Enable supplementary address: Selected
  • Enable statistics collection: Selected
  • Statistics counters: Memory-based
  • All Legacy Ethernet 10G MAC Interfaces options: Selected
For the design example with the IEEE 1588v2 feature, the following additional parameters are configured:
  • Enable time stamping: Selected
  • Enable PTP one-step clock support: Selected
  • Timestamp fingerprint width: 4
  • Time Of Day format: Enable both 96b and 64b Time of Day Format
PHY The 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP.
Transceiver Reset Controller The Transceiver PHY Reset Controller IP core. Resets the transceiver.
Avalon® -MM Mux Transceiver Reconfig Provides the transceiver reconfig block and system console access to the PHY's Avalon® -MM interface.
Transceiver Reconfig Reconfigures the transceiver channel speed from 1 Gbps to 2.5 Gbps, and vice versa.
ATX PLL

Generates a TX serial clock for the Arria® V 2.5G transceiver.

fPLL

Generates a TX serial clock for the Arria® V 1G transceiver.

Design Components for the IEEE 1588v2 Feature
IO PLL Generates the clocks for the 1588 design components.
Master TOD The master time-of-day (TOD) for all channels.
TOD Synch Synchronizes the master TOD to all local TODs.
Local TOD The TOD for each channel.
Master Pulse Per Second Returns pulse per second (pps) for all channels.
Pulse Per Second Returns pulse per second (pps) for each channel.
PTP Packet Classifier Decodes the packet type of incoming PTP packets and returns the decoded information to the LL 10GbE MAC Intel® FPGA IP core.
Level Two Title