AN 757: 1G/2.5G Ethernet Design Examples

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ID 683753
Date 11/12/2018
Public
Document Table of Contents
Document Table of Contents x
AN 757: 1G/2.5G Ethernet Design Examples
AN 757: 1G/2.5G Ethernet Design Examples x
Features Hardware and Software Requirements Functional Description Using the Design Example Simulation Hardware Testing Interface Signals Configuration Registers Document Revision History for AN 757: 1G/2.5G Ethernet Design Examples
Functional Description x
Design Components Reset Scheme Clocking Scheme
Simulation x
Testbench Using the Simulator Test Case—Design Example without the IEEE 1588v2 Feature
Hardware Testing x
Setup Test Procedure
Interface Signals x
Clock and Reset Interface Signals Avalon-MM Interface Signals Avalon-ST Interface Signals PHY Interface Signals IEEE 1588v2 Timestamp Interface Signals Packet Classifier Interface Signals TOD Interface Signals
Configuration Registers x
Transceiver Reconfiguration
AN 757: 1G/2.5G Ethernet Design Examples

Avalon-ST Interface Signals

Table 6.   Avalon-ST Interface Signals
Signal Direction Width Description
avalon_st_tx_startofpacket[] In 2 Assert this signal to indicate the beginning of the TX data.
avalon_st_tx_endofpacket[] In 2 Assert this signal to indicate the end of the TX data.
avalon_st_tx_valid[] In 2 Assert this signal to indicate that avalon_st_tx_data[] and other signals on this interface are valid.
avalon_st_tx_ready[] Out 2 When asserted, indicates that the MAC IP core is ready to accept data. The reset value of this signal is non-deterministic.
avalon_st_tx_error[] In 2 Assert this signal to indicate that the current TX packet contains errors.
avalon_st_tx_data[][] In [2][32] TX data from the client.
avalon_st_tx_empty[][] In [2][2] Use this signal to specify the number of empty bytes in the cycle that contain the end of the TX data.

0x0=All bytes are valid.

0x1=The last byte is invalid.

0x2=The last two bytes are invalid.

0x3=The last three bytes are invalid.

avalon_st_rx_startofpacket[] Out 2 When asserted, indicates the beginning of the RX data.
avalon_st_rx_endofpacket[] Out 2 When asserted, indicates the end of the RX data.
avalon_st_rx_valid[] Out 2 When asserted, indicates that the avalon_st_rx_ data[] signal and other signals on this interface are valid.
avalon_st_rx_ready[] In 2 Assert this signal when the client is ready to accept data.
avalon_st_rx_error[][] Out [2][6] When set to 1, the respective bits indicate an error type:
  • Bit 0—PHY error. For 10 Gbps, the data on xgmii_rx_data contains a control error character (FE). For 10 Mbps,100 Mbps,1 Gbps, gmii_rx_err or mii_rx_err is asserted.
  • Bit 1—CRC error. The computed CRC value differs from the received CRC.
  • Bit 2—Undersized frame. The receive frame length is less than 64 bytes.
  • Bit 3—Oversized frame. The receive frame length is more than MAX_FRAME_SIZE.
  • Bit 4—Payload length error. The actual frame payload length is different from the value in the length/type field.
  • Bit 5—Overflow error. The receive FIFO buffer is full while it is still receiving data from the MAC IP core.
avalon_st_rx_data[][] Out [2][32] RX data to the client.
avalon_st_rx_empty[][] Out [2][2] Contains the number of empty bytes during the cycle that contain the end of the RX data.
avalon_st_tx_status_valid[] Out 2 When asserted, this signal qualifies the avalon_st_txstatus_data[] and avalon_st_txstatus_error[] signals.
avalon_st_tx_status_data[][] Out [2][40] Contains information about the TX frame.
  • Bits 0 to 15: Payload length.
  • Bits 16 to 31: Packet length.
  • Bit 32: When set to 1, indicates a stacked VLAN frame.
  • Bit 33: When set to 1, indicates a VLAN frame.
  • Bit 34: When set to 1, indicates a control frame.
  • Bit 35: When set to 1, indicates a pause frame.
  • Bit 36: When set to 1, indicates a broadcast frame.
  • Bit 37: When set to 1, indicates a multicast frame.
  • Bit 38: When set to 1, indicates a unicast frame.
  • Bit 39: When set to 1, indicates a PFC frame.
avalon_st_tx_status_error[][] Out [2][7] When set to 1, the respective bit indicates the following error type in the RX frame.
  • Bit 0: Undersized frame.
  • Bit 1: Oversized frame.
  • Bit 2: Payload length error.
  • Bit 3: Unused.
  • Bit 4: Underflow.
  • Bit 5: Client error.
  • Bit 6: Unused.
The error status is invalid when an overflow occurs.
avalon_st_rx_status_valid[] Out 2 When asserted, this signal qualifies the avalon_st_txstatus_data[] and avalon_st_txstatus_error[] signals. The MAC IP core asserts this signal in the same clock cycle the avalon_st_rx_endofpacket signal is asserted.
avalon_st_rx_status_data[][] Out [2][40] Contains information about the RX frame.
  • Bits 0 to 15: Payload length.
  • Bits 16 to 31: Packet length.
  • Bit 32: When set to 1, indicates a stacked VLAN frame.
  • Bit 33: When set to 1, indicates a VLAN frame.
  • Bit 34: When set to 1, indicates a control frame.
  • Bit 35: When set to 1, indicates a pause frame.
  • Bit 36: When set to 1, indicates a broadcast frame.
  • Bit 37: When set to 1, indicates a multicast frame.
  • Bit 38: When set to 1, indicates a unicast frame.
  • Bit 39: When set to 1, indicates a PFC frame.
avalon_st_rx_status_error[][] Out [2][7] When set to 1, the respective bit indicates the following error type in the RX frame.
  • Bit 0: Undersized frame.
  • Bit 1: Oversized frame.
  • Bit 2: Payload length error.
  • Bit 3: Unused.
  • Bit 4: Underflow.
  • Bit 5: Client error.
  • Bit 6: Unused.
The error status is invalid when an overflow occurs.
avalon_st_pause_data[][] In [2][2] This signal takes effect when the register bits, tx_pauseframe_enable[2:1], are both set to the default value 0.

Set this signal to the following values to trigger the corresponding actions.

  • 0x0: Stops pause frame generation.
  • 0x1: Generates an XON pause frame.
  • 0x2: Generates an XOFF pause frame. The MAC IP core sets the pause quanta field in the pause frame to the value in the tx_pauseframe_quanta register.
  • 0x3: Reserved.
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