Floating-Point IP Cores User Guide

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Date 10/27/2021
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Document Table of Contents
Document Table of Contents x
1. About Floating-Point IP Cores 2. FP_ACC_CUSTOM Intel® FPGA IP or Floating Point Custom Accumulator Intel® FPGA IP Core 3. ALTFP_ADD_SUB IP Core 4. ALTFP_DIV IP Core 5. ALTFP_MULT IP Core 6. ALTFP_SQRT 7. ALTFP_EXP IP Core 8. ALTFP_INV IP Core 9. ALTFP_INV_SQRT IP Core 10. ALTFP_LOG 11. ALTFP_ATAN IP Core 12. ALTFP_SINCOS IP Core 13. ALTFP_ABS IP Core 14. ALTFP_COMPARE IP Core 15. ALTFP_CONVERT IP Core 16. FP_FUNCTIONS Intel® FPGA IP or Floating Point Functions Intel® FPGA IP Core 17. Floating-Point IP Cores User Guide Document Archives 18. Document Revision History for the Floating-Point IP Cores User Guide
1. About Floating-Point IP Cores x
1.1. List of Floating-Point IP Cores 1.2. Installing and Licensing Intel® FPGA IP Cores 1.3. Design Flow 1.4. Upgrading IP Cores 1.5. Floating-Point IP Cores General Features 1.6. IEEE-754 Standard for Floating-Point Arithmetic 1.7. Non-IEEE-754 Standard Format 1.8. Floating-Points IP Cores Output Latency 1.9. Floating-Point IP Cores Design Example Files 1.10. VHDL Component Declaration 1.11. VHDL LIBRARY-USE Declaration
1.3. Design Flow x
1.3.1. IP Catalog and Parameter Editor 1.3.2. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 1.3.3. Generating IP Cores ( Intel® Quartus® Prime Standard Edition)
1.3.1. IP Catalog and Parameter Editor x
1.3.1.1. The Parameter Editor
1.3.2. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) x
1.3.2.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
1.4. Upgrading IP Cores x
1.4.1. Migrating IP Cores to a Different Device
1.6. IEEE-754 Standard for Floating-Point Arithmetic x
1.6.1. Floating-Point Formats 1.6.2. Special Case Numbers 1.6.3. Rounding
1.6.1. Floating-Point Formats x
1.6.1.1. Single-Precision Format 1.6.1.2. Double-Precision Format 1.6.1.3. Single-Extended Precision Format
2. FP_ACC_CUSTOM Intel® FPGA IP or Floating Point Custom Accumulator Intel® FPGA IP Core x
2.1. FP_ACC_CUSTOM Intel® FPGA IP or Floating Point Custom Accumulator Intel® FPGA IP Features 2.2. FP_ACC_CUSTOM Intel® FPGA IP or Floating Point Custom Accumulator Intel® FPGA IP Output Latency 2.3. FP_ACC_CUSTOM Intel® FPGA IP Resource Utilization and Performance 2.4. FP_ACC_CUSTOM Intel® FPGA IP or Floating Point Custom Accumulator Intel® FPGA IP Signals 2.5. FP_ACC_CUSTOM Intel® FPGA IP or Floating Point Custom Accumulator Intel® FPGA IP Parameters
3. ALTFP_ADD_SUB IP Core x
3.1. ALTFP_ADD_SUB Features 3.2. ALTFP_ADD_SUB Output Latency 3.3. ALTFP_ADD_SUB Truth Table 3.4. ALTFP_ADD_SUB Resource Utilization and Performance 3.5. ALTFP_ADD_SUB Design Example: Addition of Double-Precision Format Numbers 3.6. ALTFP_ADD_SUB Signals 3.7. ALTFP_ADD_SUB Parameters
3.5. ALTFP_ADD_SUB Design Example: Addition of Double-Precision Format Numbers x
3.5.1. ALTFP_ADD_SUM Design Example: Understanding the Simulation Results
4. ALTFP_DIV IP Core x
4.1. ALTFP_DIV Features 4.2. ALTFP_DIV Output Latency 4.3. ALTFP_DIV Truth Table 4.4. ALTFP_DIV Resource Utilization and Performance 4.5. ALTFP_DIV Design Example: Division of Single-Precision 4.6. ALTFP_DIV Signals 4.7. ALTFP_DIV Parameters
4.5. ALTFP_DIV Design Example: Division of Single-Precision x
4.5.1. ALTFP_DIV Design Example: Understanding the Simulation Results
5. ALTFP_MULT IP Core x
5.1. ALTFP_MULT IP Core Features 5.2. ALTFP_MULT Output Latency 5.3. ALTFP_MULT Truth Table 5.4. ALTFP_MULT Resource Utilization and Performance 5.5. ALTFP_MULT Design Example: Multiplication of Double-Precision Format Numbers 5.6. Parameters 5.7. ALTFP_MULT Signals
5.5. ALTFP_MULT Design Example: Multiplication of Double-Precision Format Numbers x
5.5.1. ALTFP_MULT Design Example: Understanding the Simulation Waveform
6. ALTFP_SQRT x
6.1. ALTFP_SQRT Features 6.2. Output Latency 6.3. ALTFP_SQRT Truth Table 6.4. ALTFP_SQRT Resource Utilization and Performance 6.5. ALTFP_SQRT Design Example: Square Root of Single-Precision Format Numbers 6.6. ALTFP_SQRT Signals 6.7. ALTFP_SQRT Parameters
6.5. ALTFP_SQRT Design Example: Square Root of Single-Precision Format Numbers x
6.5.1. ALTFP_SQRT Design Example: Understanding the Simulation Results
7. ALTFP_EXP IP Core x
7.1. ALTFP_EXP Features 7.2. Output Latency 7.3. ALTFP_EXP Truth Table 7.4. ALTFP_EXP Resource Utilization and Performance 7.5. ALTFP_EXP Design Example: Exponential of Single-Precision Format Numbers 7.6. ALTFP_EXP Signals 7.7. ALTFP_EXP Parameters
7.5. ALTFP_EXP Design Example: Exponential of Single-Precision Format Numbers x
7.5.1. ALTFP_EXP Design Example: Understanding the Simulation Results
8. ALTFP_INV IP Core x
8.1. ALTFP_INV Features 8.2. Output Latency 8.3. ALTFP_INV Truth Table 8.4. ALTFP_INV Resource Utilization and Performance 8.5. ALTFP_INV Design Example: Inverse of Single-Precision Format Numbers 8.6. Ports 8.7. Parameters
8.5. ALTFP_INV Design Example: Inverse of Single-Precision Format Numbers x
8.5.1. ALTFP_INV Design Example: Understanding the Simulation Results
9. ALTFP_INV_SQRT IP Core x
9.1. ALTFP_INV_SQRT Features 9.2. Output Latency 9.3. ALTFP_INV_SQRT Truth Table 9.4. ALTFP_INV_SQRT Resource Utilization and Performance 9.5. ALTFP_INV_SQRT Design Example: Inverse Square Root of Single-Precision Format Numbers 9.6. Ports 9.7. Parameters
9.5. ALTFP_INV_SQRT Design Example: Inverse Square Root of Single-Precision Format Numbers x
9.5.1. ALTFP_INV_SQRT Design Example: Understanding the Simulation Results
10. ALTFP_LOG x
10.1. ALTFP_LOG Features 10.2. Output Latency 10.3. ALTFP_LOG Truth Table 10.4. ALTFP_LOG Resource Utilization and Performance 10.5. ALTFP_LOG Design Example: Natural Logarithm of Single-Precision Format Numbers 10.6. Signals 10.7. Parameters
10.5. ALTFP_LOG Design Example: Natural Logarithm of Single-Precision Format Numbers x
10.5.1. ALTFP_LOG Design Example: Understanding the Simulation Results
11. ALTFP_ATAN IP Core x
11.1. Output Latency 11.2. ALTFP_ATAN Features 11.3. ALTFP_ATAN Resource Utilization and Performance 11.4. Ports 11.5. ALTFP_ATAN Parameters
12. ALTFP_SINCOS IP Core x
12.1. ALTFP_SINCOS Features 12.2. Output Latency 12.3. ALTFP_SINCOS Resource Utilization and Performance 12.4. ALTFP_SINCOS Signals 12.5. ALTFP_SINCOS Parameters
13. ALTFP_ABS IP Core x
13.1. ALTFP_ABS Features 13.2. ALTFP_ABS Output Latency 13.3. ALTFP_ABS Resource Utilization and Performance 13.4. ALTFP_ABS Design Example: Absolute Value of Multiplication Results 13.5. ALTFP_ABS Signals 13.6. ALTFP_ABS Parameters
13.4. ALTFP_ABS Design Example: Absolute Value of Multiplication Results x
13.4.1. ALTFP_ABS Design Example: Understanding the Simulation Results
14. ALTFP_COMPARE IP Core x
14.1. ALTFP_COMPARE Features 14.2. ALTFP_COMPARE Output Latency 14.3. ALTFP_COMPARE Resource Utilization and Performance 14.4. ALTFP_COMPARE Design Example: Comparison of Single-Precision Format Numbers 14.5. ALTFP_COMPARE Signals 14.6. ALTFP_COMPARE Parameters
14.4. ALTFP_COMPARE Design Example: Comparison of Single-Precision Format Numbers x
14.4.1. ALTFP_COMPARE Design Example: Understanding the Simulation Results
15. ALTFP_CONVERT IP Core x
15.1. ALTFP_CONVERT Features 15.2. ALTFP_CONVERT Conversion Operations 15.3. ALTFP_CONVERT Output Latency 15.4. ALTFP_CONVERT Resource Utilization and Performance 15.5. ALTFP_CONVERT Design Example: Convert Double-Precision Floating-Point Format Numbers 15.6. ALTFP_CONVERT Signals 15.7. ALTFP_CONVERT Parameters
15.5. ALTFP_CONVERT Design Example: Convert Double-Precision Floating-Point Format Numbers x
15.5.1. ALTFP_CONVERT Design Example: Understanding the Simulation Results
16. FP_FUNCTIONS Intel® FPGA IP or Floating Point Functions Intel® FPGA IP Core x
16.1. FP_FUNCTIONS Intel® FPGA IP or Floating Point Functions Intel® FPGA IP Features 16.2. FP_FUNCTIONS Intel® FPGA IP or Floating Point Functions Intel® FPGA IP Output Latency 16.3. FP_FUNCTIONS Intel® FPGA IP or Floating Point Functions Intel® FPGA IP Target Frequency 16.4. FP_FUNCTIONS Intel® FPGA IP or Floating Point Functions Intel® FPGA IP Combined Target 16.5. FP_FUNCTIONS Intel® FPGA IP Resource Utilization and Performance 16.6. FP_FUNCTIONS Intel® FPGA IP Signals 16.7. FP_FUNCTIONS Intel® FPGA IP Parameters
1. About Floating-Point IP Cores
2. FP_ACC_CUSTOM Intel® FPGA IP or Floating Point Custom Accumulator Intel® FPGA IP Core
3. ALTFP_ADD_SUB IP Core
4. ALTFP_DIV IP Core
5. ALTFP_MULT IP Core
6. ALTFP_SQRT
7. ALTFP_EXP IP Core
8. ALTFP_INV IP Core
9. ALTFP_INV_SQRT IP Core
10. ALTFP_LOG
11. ALTFP_ATAN IP Core
12. ALTFP_SINCOS IP Core
13. ALTFP_ABS IP Core
14. ALTFP_COMPARE IP Core
15. ALTFP_CONVERT IP Core
16. FP_FUNCTIONS Intel® FPGA IP or Floating Point Functions Intel® FPGA IP Core
17. Floating-Point IP Cores User Guide Document Archives
18. Document Revision History for the Floating-Point IP Cores User Guide

16.5. FP_FUNCTIONS Intel® FPGA IP Resource Utilization and Performance

These tables list the resource utilization and performance information for the FP_Functions Intel® FPGA IP core. The information was derived using the Intel® Quartus® Prime software version 14.1. The frequency target was set to 200 MHz.
Table 93.  Arithmetic
Family Function Precision Latency fMAX ALMs M10K M20K DSP Blocks Logic Registers
Primary Secondary
Arria V (5AGXFB3H4F40C5) Abs Single 0 — 33 0 — 0 0 0
Double 0 — 65 0 — 0 0 0
Add Single 9 233.1 360 0 — 0 507 29
Double 12 251.95 886 0 — 0 1064 61
AddSubtract Single 9 249.31 477 0 0 0 651 63
Double 12 252.46 1161 0 0 0 1713 91
Cube Root Single 9 275.18 132 6 — 2 132 20
Double 24 185.77 634 17 — 10 1297 58
Divide Single 18 249 456 5 — 4 771 100
Double 35 185.29 1409 39 — 15 3035 138
Exp base 10 Single 16 212.72 547 3 — 2 675 18
Double 31 185.77 2194 0 — 10 2626 56
Arria V (5AGXFB3H4F40C5) Exp base 2 Single 7 236.41 345 0 — 2 214 19
Double 21 185.84 932 0 — 10 1324 51
Exp base e Single 14 217.96 718 0 — 2 597 46
Double 28 185.87 2134 0 — 10 2398 46
Reciprocal Single 12 253.16 210 4 — 3 294 26
Double 30 185.29 877 9 — 14 1764 105
Reciprocal Square Root Single 7 267.52 118 4 — 2 141 14
Double 20 185.74 539 13 — 9 1210 52
LDExp Single 2 367.92 69 0 — 0 85 0
Double 2 359.32 100 0 — 0 146 0
Arria V (5AGXFB3H4F40C5) Log base 10 Single 16 250 379 4 -- 3 622 65
Double 34 186.12 1,380 40 -- 11 3,025 143
Arria V (5AGXFB3H4F40C5) Log(1+x) Single 21 222.77 766 4 -- 3 1,171 82
Double 43 185.94 2,361 40 -- 14 4,702 183
Log base 2 Single 16 232.29 350 4 -- 3 584 64
Double 37 185.32 1,342 13 -- 17 3,156 121
Log base e Single 16 248.57 379 4 -- 3 616 57
Double 35 185.84 1,422 40 -- 13 3,066 147
Multiply Single 5 281.14 156 0 -- 1 152 6
Double 7 186.01 339 0 -- 4 549 13
Arria V (5AGXFB3H4F40C5) Power Single 45 201.82 1,347 11 -- 14 2,410 165
Double 82 185.43 4,195 20 -- 38 8,149 266
Square Root Single 8 261.92 119 3 -- 2 174 13
Double 21 185.94 548 8 -- 9 1,225 44
Subtract Single 9 232.67 363 0 -- 0 505 32
Double 12 257.07 884 0 -- 0 1,064 61
Cyclone V (5CGXFC7D6F31C7) Abs Single 0 -- 33 0 -- 0 0 0
Double 0 -- 65 0 -- 0 0 0
Add Single 12 225.94 403 0 -- 0 562 35
Double 20 208.99 932 0 -- 0 1,813 72
AddSubtract Single 12 224.67 509 0 -- 0 805 65
Double 20 211.55 1,197 0 -- 0 2,647 120
Cube Root Single 10 230.47 131 6 -- 2 213 11
Double 34 212.49 890 17 -- 10 1,991 54
Divide Single 20 232.61 466 5 -- 4 991 62
Double 51 201.01 1,782 41 -- 15 4,317 165
Cyclone V (5CGXFC7D6F31C7) Exp base 10 Single 20 217.58 552 3 -- 2 905 32
Double 52 212.77 2,317 0 -- 10 4,287 122
Exp base 2 Single 9 211.33 352 0 -- 2 314 13
Double 36 219.3 1,128 0 -- 10 2,364 87
Exp base e Single 17 207.68 698 0 -- 2 860 31
Double 50 198.85 2,309 0 -- 10 4,300 126
Reciprocal Single 14 230.95 245 4 -- 3 378 26
Double 44 207.43 1,201 9 -- 14 2,694 94
Reciprocal Square Root Single 9 233.37 137 4 -- 2 223 25
Double 30 250 782 13 -- 9 1,932 46
Cyclone V (5CGXFC7D6F31C7) LDExp Single 2 346.02 69 0 -- 0 87 1
Double 3 357.91 104 0 -- 0 215 0
Log base 10 Single 22 203.33 486 4 -- 3 1,066 47
Double 49 196.97 1,888 40 -- 11 4,483 153
Log(1+x) Single 29 191.5 944 4 -- 3 1,844 105
Double 62 168.27 3,012 40 -- 14 6,899 210
Log base 2 Single 20 202.1 413 4 -- 3 918 50
Double 54 194.21 1,898 13 -- 17 4,732 151
Cyclone V (5CGXFC7D6F31C7) Log base e Single 22 181.42 482 4 -- 3 1,058 45
Double 50 196.27 1,941 40 -- 13 4,611 197
Multiply Single 6 268.6 159 0 -- 1 223 2
Double 11 205.17 431 0 -- 4 970 18
Power Single 62 181.19 1,778 11 -- 14 3,562 154
Double 127 186.53 5,411 22 -- 38 12,361 325
Square Root Single 8 219.15 126 3 -- 2 205 12
Double 31 250 822 8 -- 9 2,056 55
Subtract Single 12 232.07 399 0 -- 0 566 42
Double 20 204.25 918 0 -- 0 1,839 60
Stratix V (5SGXEA7K2F40C2) Abs Single 0 -- 33 -- 0 0 0 0
Double 0 -- 65 -- 0 0 0 0
Add Single 5 364.83 366 -- 0 0 299 19
Double 7 329.49 834 -- 0 0 801 53
AddSubtract Single 5 354.74 489 -- 0 0 411 29
Double 7 338.41 1,106 -- 0 0 1,039 134
Cube Root Single 8 420.17 114 -- 5 2 124 11
Double 20 277.7 520 -- 11 10 997 17
Divide Single 13 363.5 377 -- 3 4 591 71
Double 23 270.86 1,091 -- 20 15 2,274 120
Exp base 10 Single 11 292.4 486 -- 3 2 417 12
Double 22 271.74 2,033 -- 0 10 1,761 48
Stratix V (5SGXEA7K2F40C2) Exp base 2 Single 5 387.3 351 -- 0 2 160 1
Double 17 279.56 897 -- 0 10 995 27
Exp base e Single 8 284.09 653 -- 0 2 350 18
Double 23 268.38 2,043 -- 0 10 1,710 44
Reciprocal Single 9 279.33 199 -- 3 3 211 13
Double 22 241.31 764 -- 9 14 1,391 49
Reciprocal Square Root Single 6 420.52 105 -- 3 2 129 9
Double 17 271.37 449 -- 8 9 1,009 47
LDExp Single 0 -- 67 -- 0 0 0 0
Double 0 717.36 99 -- 0 0 66 0
Log base 10 Single 11 359.58 358 -- 3 3 443 29
Double 23 271.96 1,077 -- 20 11 2,252 101
Stratix V (5SGXEA7K2F40C2) Log(1+x) Single 15 338.64 748 -- 3 3 905 55
Double 27 280.98 1,911 -- 20 13 3,301 122
Log base 2 Single 11 340.37 304 -- 3 3 392 15
Double 27 258.33 1,053 -- 8 16 2,241 110
Log base e Single 11 351.86 359 -- 3 3 439 35
Double 23 270.49 1,071 -- 20 13 2,210 94
Multiply Single 3 399.52 136 -- 0 1 72 1
Double 4 250.75 312 -- 0 4 237 5
Power Single 31 261.23 1,171 -- 8 12 1,492 83
Double 60 267.81 3,555 -- 13 37 5,347 244
Square Root Single 6 393.7 112 -- 3 2 129 7
Double 17 274.12 458 -- 8 9 1,019 41
Subtract Single 5 320.41 360 -- 0 0 299 14
Double 7 338.52 835 -- 0 0 801 51
Arria 10 (10AX115H4F34I3SP) Abs Single 0 -- 33 -- 0 0 0 0
Double 0 -- 65 -- 0 0 0 0
Add Single 4 296.4 49 -- 0 1 0 0
Double 7 296.3 840 -- 0 0 779 67
AddSubtract Single 5 319.39 483 -- 0 0 408 37
Double 7 289.77 1,106 -- 0 0 1,006 156
Cube Root Single 10 432.9 126 -- 5 2 121 0
Double 24 282.09 594 -- 11 10 1,155 29
Divide Single 16 347.34 394 -- 3 4 561 66
Double 30 258.26 1,208 -- 20 15 2,175 136
Exp base 10 Single 14 271.37 502 -- 3 2 432 40
Double 29 242.42 2,185 -- 0 10 1,683 90
Arria 10 (10AX115H4F34I3SP) Exp base 2 Single 7 317.86 370 -- 0 2 124 9
Double 22 251.45 906 -- 0 10 1,172 47
Exp base e Single 26 365.36 298 -- 3 6 137 11
Double 28 260.42 2,156 -- 0 10 1,724 93
Reciprocal Single 12 278.94 225 -- 3 3 172 3
Double 27 260.89 824 -- 9 14 1,448 100
Reciprocal Square Root Single 8 418.94 117 -- 3 2 130 1
Double 22 243.43 523 -- 8 9 950 37
LDExp Single 0 -- 68 -- 0 0 0 0
Double 0 -- 99 -- 0 0 66 0
Log base 10 Single 15 293.69 364 -- 3 3 441 42
Double 28 272.03 1,158 -- 20 11 2,095 214
Log(1+x) Single 18 301.3 747 -- 3 3 882 79
Double 32 251.95 2,018 -- 20 13 3,019 248
Arria 10 (10AX115H4F34I3SP) Log base 2 Single 14 275.79 316 -- 3 3 402 3
Double 32 271.96 1,173 -- 8 16 2,372 132
Log base e Single 29 378.07 297 -- 3 9 315 6
Double 29 256.54 1,219 -- 20 13 2,338 152
Multiply Single 3 288.4 49 -- 0 1 0 0
Double 5 288.35 312 -- 0 4 236 26
Power Single 40 262.12 1,335 -- 8 14 1,523 127
Double 73 237.7 3,957 -- 13 37 5,362 305
Square Root Single 8 432.9 124 -- 3 2 118 8
Double 22 249.25 539 -- 8 9 1,000 34
Subtract Single 4 296.9 49 -- 0 1 0 0
Double 7 296.82 842 -- 0 0 783 76
Table 94.  Trigonometry
Family Function Precision Scale By Pi Latency fMAX ALMs M10K M20K DSP Blocks Logic Registers
Primary Secondary
Arria V (5AGXFB3H4F40C5) Arccos Single 0 35 217.77 768 9 -- 8 1,289 94
Single 1 39 216.45 819 9 -- 9 1,383 92
Double 0 76 185.7 2,917 27 -- 37 6,489 230
Double 1 83 184.2 3,120 27 -- 40 6,899 198
Arcsin Single 0 29 215.8 652 9 -- 8 1,069 93
Single 1 34 222.32 747 9 -- 9 1,178 80
Double 0 66 185.32 2,762 29 -- 41 6,365 171
Double 1 72 184.16 2,963 29 -- 44 6,696 200
Arctan Single 0 27 232.29 603 7 -- 6 937 77
Single 1 31 230.73 664 7 -- 7 1,034 89
Double 0 65 185.7 2,047 23 -- 31 4,535 164
Double 1 71 185.6 2,229 23 -- 34 4,854 174
Arria V (5AGXFB3H4F40C5) Arctan2 Single 0 43 230.2 1,013 11 -- 9 1,719 128
Single 1 43 230.2 1,013 11 -- 9 1,719 128
Double 0 92 184.2 3,195 44 -- 43 6,822 285
Double 1 92 184.2 3,195 44 -- 43 6,822 285
Cos Single 0 25 205.3 768 5 -- 6 1,563 120
Single 1 12 242.13 490 0 -- 3 475 36
Double 0 45 184.2 2,879 34 -- 33 5,973 244
Double 1 29 185.87 1,719 0 -- 13 2,499 92
Arria V (5AGXFB3H4F40C5) Sin Single 0 26 223.51 964 5 -- 6 1,439 110
Single 1 12 240.56 585 0 -- 3 563 66
Double 0 46 184.16 3,019 36 -- 33 6,308 249
Double 1 29 185.77 1,748 0 -- 14 2,699 92
Tan Single 0 38 221.78 1,368 12 -- 12 2,625 163
Single 1 25 231.43 1,297 4 -- 10 1,512 140
Double 0 68 185.56 5,211 56 -- 65 10,670 530
Double 1 52 184.16 3,874 26 -- 43 6,896 238
Cyclone V (5CGXFC7D6F31C7) Arccos Single 0 42 217.2 857 9 -- 8 1,701 107
Single 1 47 196.27 943 9 -- 9 1,887 104
Double 0 113 196.5 3,957 31 -- 37 9,739 343
Double 1 123 210.17 4,218 31 -- 40 10,353 333
Arcsin Single 0 35 222.62 757 9 -- 8 1,464 65
Single 1 40 215.19 844 9 -- 9 1,627 111
Double 0 101 201.65 3,816 31 -- 41 9,709 334
Double 1 112 197.71 4,046 31 -- 44 10,383 260
Arctan Single 0 33 227.58 706 7 -- 6 1,266 92
Single 1 38 206.31 787 7 -- 7 1,434 90
Double 0 98 188.79 2,920 24 -- 31 7,154 297
Double 1 109 180.41 3,196 24 -- 34 7,875 297
Cyclone V (5CGXFC7D6F31C7) Arctan2 Single 0 51 206.14 1,153 11 -- 9 2,013 149
Single 1 51 206.14 1,153 11 -- 9 2,013 149
Double 0 144 191.17 4,589 46 -- 43 10,740 417
Double 1 144 191.17 4,589 46 -- 43 10,740 417
Cos Single 0 32 174.67 959 5 -- 6 2,258 110
Single 1 15 212.99 517 0 -- 3 702 25
Double 0 75 182.75 3,751 34 -- 33 9,177 352
Double 1 50 212.68 1,985 0 -- 13 3,914 169
Sin Single 0 33 191.61 1,086 5 -- 6 2,394 132
Single 1 14 207.81 579 0 -- 3 783 39
Double 0 75 196.39 3,787 38 -- 33 9,545 284
Double 1 49 206.53 2,165 0 -- 14 4,336 177
Tan Single 0 46 185.74 1,655 12 -- 12 3,738 200
Single 1 29 205.47 1,283 4 -- 10 2,142 102
Double 0 112 194.7 7,052 58 -- 65 16,793 607
Double 1 89 197.24 5,327 26 -- 43 11,741 376
Stratix V (5SGXEA7K2F40C2) Arccos Single 0 23 291.46 753 -- 9 8 801 34
Single 1 27 288.43 823 -- 9 9 891 27
Double 0 53 247.46 2,380 -- 27 37 4,435 145
Double 1 58 233.15 2,570 -- 27 40 4,717 121
Arcsin Single 0 20 290.61 598 -- 9 8 698 19
Single 1 23 294.99 678 -- 9 9 800 21
Double 0 47 237.25 2,235 -- 27 40 4,407 89
Double 1 52 240.33 2,411 -- 27 43 4,621 134
Arctan Single 0 20 293.6 544 -- 6 6 646 53
Single 1 23 290.7 620 -- 6 7 715 50
Double 0 47 241.72 1,837 -- 18 30 3,424 145
Double 1 52 247.34 2,002 -- 18 33 3,654 126
Arctan2 Single 0 31 288.35 890 -- 9 9 1,277 71
Single 1 31 288.35 890 -- 9 9 1,277 71
Double 0 69 239.23 2,983 -- 29 42 5,530 212
Double 1 69 239.23 2,983 -- 29 42 5,530 212
Stratix V (5SGXEA7K2F40C2) Cos Single 0 17 267.02 711 -- 5 6 890 48
Single 1 8 364.83 452 -- 0 3 368 20
Double 0 33 242.25 2,529 -- 17 31 4,510 187
Double 1 21 275.48 1,608 -- 0 13 1,799 54
Sin Single 0 18 309.69 856 -- 5 6 917 74
Single 1 8 317.46 538 -- 0 3 382 10
Double 0 34 257.67 2,714 -- 19 31 4,766 229
Double 1 22 260.89 1,864 -- 0 14 1,898 104
Tan Single 0 27 272.26 1,312 -- 11 12 1,675 117
Single 1 17 295.68 1,164 -- 3 10 1,175 65
Double 0 52 268.38 4,612 -- 30 60 8,152 264
Double 1 41 260.89 3,886 -- 13 43 5,294 193
Arria 10 (10AX115H4F34I3SP) Arccos Single 0 28 270.42 703 -- 9 8 656 29
Single 1 31 261.23 705 -- 9 9 624 19
Double 0 63 257.8 2,626 -- 27 37 4,917 241
Double 1 69 255.62 2,813 -- 27 40 5,127 268
Arcsin Single 0 25 249.63 665 -- 9 8 659 18
Single 1 28 254.19 673 -- 9 9 649 30
Double 0 57 255.62 2,440 -- 29 40 4,750 213
Double 1 62 251.51 2,596 -- 29 43 4,985 190
Arctan Single 0 26 271.3 600 -- 6 6 578 32
Single 1 29 274.2 594 -- 6 7 583 22
Double 0 57 254.13 1,866 -- 22 30 3,654 171
Double 1 63 258.33 2,043 -- 22 33 3,726 253
Arctan2 Single 0 40 248.14 1,002 -- 9 9 1,258 85
Single 1 40 248.14 1,002 -- 9 9 1,258 85
Double 0 84 255.1 3,025 -- 33 42 5,675 328
Double 1 84 255.1 3,025 -- 33 42 5,675 328
Arria 10 (10AX115H4F34I3SP) Cos Single 0 21 336.93 786 -- 5 6 979 154
Single 1 11 310.37 512 -- 0 3 297 22
Double 0 39 263.92 2,702 -- 17 33 3,697 375
Double 1 29 242.19 1,698 -- 0 13 2,030 62
Sin Single 0 22 311.33 876 -- 5 6 1,003 116
Single 1 11 279.02 585 -- 0 3 330 19
Double 0 41 265.25 2,791 -- 19 33 3,902 334
Double 1 29 259.61 1,918 -- 0 14 1,943 72
Tan Single 0 34 265.6 1,359 -- 11 12 1,756 155
Single 1 23 265.89 1,268 -- 3 10 1,065 94
Double 0 64 248.14 5,107 -- 30 65 7,578 458
Double 1 53 251.7 4,002 -- 17 43 5,619 343
Table 95.  FPFXP
Family Input Precision Output Width Output Fraction Latency fMAX ALMs M10K M20K DSP Blocks Logic Registers
Primary Secondary
Arria V (5AGXFB3H4F40C5) Single 32 0 2 277.93 168 0 -- 0 75 1
32 16 2 266.1 169 0 -- 0 75 0
32 32 2 277.93 168 0 -- 0 75 1
64 0 3 226.4 291 0 -- 0 172 0
64 16 3 226.4 291 0 -- 0 172 0
64 32 3 226.4 291 0 -- 0 172 0
Double 32 0 3 332.12 197 0 -- 0 115 0
32 16 3 344.12 197 0 -- 0 115 0
32 32 3 332.12 197 0 -- 0 115 0
64 0 3 256.28 326 0 -- 0 205 4
64 16 3 256.28 326 0 -- 0 205 4
64 32 3 256.28 326 0 -- 0 205 4
Cyclone V (5CGXFC7D6F31C7) Single 32 0 3 245.04 171 0 -- 0 110 0
32 16 3 245.04 171 0 -- 0 110 0
32 32 3 245.04 171 0 -- 0 110 0
64 0 4 190.62 244 0 -- 0 269 0
64 16 4 190.62 244 0 -- 0 269 0
64 32 4 190.62 244 0 -- 0 269 0
Double 32 0 4 291.63 209 0 -- 0 160 1
32 16 4 302.94 209 0 -- 0 160 1
32 32 4 291.63 209 0 -- 0 160 1
64 0 5 207.25 329 0 -- 0 347 2
64 16 5 207.25 329 0 -- 0 347 2
64 32 5 207.25 329 0 -- 0 347 2
Stratix V (5SGXEA7K2F40C2) Single 32 0 0 717.36 168 -- 0 0 38 0
32 16 0 717.36 168 -- 0 0 38 0
32 32 0 717.36 168 -- 0 0 38 0
64 0 0 717.36 304 -- 0 0 70 0
64 16 0 717.36 304 -- 0 0 70 0
64 32 0 717.36 304 -- 0 0 70 0
Double 32 0 0 717.36 204 -- 0 0 38 0
32 16 0 717.36 204 -- 0 0 38 0
32 32 0 717.36 204 -- 0 0 38 0
64 0 2 456 329 -- 0 0 134 1
64 16 2 456 329 -- 0 0 134 1
64 32 2 456 329 -- 0 0 134 1
Arria 10 (10AX115H4F34I3SP) Single 32 0 0 -- 168 -- 0 0 38 0
32 16 0 -- 168 -- 0 0 38 0
32 32 0 -- 168 -- 0 0 38 0
64 0 0 -- 304 -- 0 0 70 0
64 16 0 -- 304 -- 0 0 70 0
64 32 0 -- 304 -- 0 0 70 0
Double 32 0 0 -- 203 -- 0 0 38 0
32 16 0 -- 203 -- 0 0 38 0
32 32 0 -- 203 -- 0 0 38 0
64 0 2 407.33 328 -- 0 0 134 0
64 16 2 407.33 328 -- 0 0 134 0
64 32 2 407.33 328 -- 0 0 134 0
Table 96.  FXPFP
Family Input Width Input Fraction Output Precision Latency fMAX ALMs M10K M20K DSP Blocks Logic Registers
Primary Secondary
Arria V (5AGXFB3H4F40C5) 32 0 Single 6 283.61 154 0 -- 0 195 14
32 0 Double 5 328.19 165 0 -- 0 180 17
32 16 Single 6 283.61 154 0 -- 0 195 14
32 16 Double 5 328.19 165 0 -- 0 180 17
32 32 Single 6 293 152 0 -- 0 193 13
32 32 Double 5 336.59 159 0 -- 0 180 16
64 0 Single 7 282.01 217 0 -- 0 297 16
64 0 Double 7 256.48 330 0 -- 0 451 18
64 16 Single 7 282.01 217 0 -- 0 297 16
64 16 Double 7 256.48 330 0 -- 0 451 18
64 32 Single 7 282.01 217 0 -- 0 297 16
64 32 Double 7 256.48 330 0 -- 0 451 18
Cyclone V (5CGXFC7D6F31C7) 32 0 Single 8 230.04 168 0 -- 0 264 21
32 0 Double 7 292.74 180 0 -- 0 258 23
32 16 Single 8 230.04 168 0 -- 0 264 21
32 16 Double 7 292.74 180 0 -- 0 258 23
32 32 Single 8 237.14 166 0 -- 0 262 20
32 32 Double 7 268.6 179 0 -- 0 258 29
64 0 Single 9 248.51 219 0 -- 0 391 18
64 0 Double 10 176.87 338 0 -- 0 648 18
64 16 Single 9 248.51 219 0 -- 0 391 18
64 16 Double 10 176.87 338 0 -- 0 648 18
64 32 Single 9 248.51 219 0 -- 0 391 18
64 32 Double 10 176.87 338 0 -- 0 648 18
Stratix V (5SGXEA7K2F40C2) 32 0 Single 3 579.71 148 -- 0 0 97 1
32 0 Double 2 547.95 161 -- 0 0 72 1
32 16 Single 3 550.66 148 -- 0 0 97 1
32 16 Double 2 536.19 160 -- 0 0 72 0
32 32 Single 3 558.66 145 -- 0 0 96 1
32 32 Double 2 496.28 154 -- 0 0 72 1
64 0 Single 3 454.55 194 -- 0 0 125 0
64 0 Double 3 434.22 304 -- 0 0 194 3
64 16 Single 3 454.55 194 -- 0 0 125 0
64 16 Double 3 434.22 304 -- 0 0 194 3
64 32 Single 3 454.55 194 -- 0 0 125 0
64 32 Double 3 434.22 304 -- 0 0 194 3
Arria 10 (10AX115H4F34I3SP) 32 0 Single 3 464.9 147 -- 0 0 97 0
32 0 Double 2 458.93 161 -- 0 0 72 0
32 16 Single 3 464.9 147 -- 0 0 97 0
32 16 Double 2 432.15 160 -- 0 0 72 0
32 32 Single 3 451.67 145 -- 0 0 96 0
32 32 Double 2 419.99 154 -- 0 0 72 0
64 0 Single 3 417.54 193 -- 0 0 124 3
64 0 Double 3 407.33 305 -- 0 0 193 3
64 16 Single 3 417.54 193 -- 0 0 124 3
64 16 Double 3 407.33 305 -- 0 0 193 3
64 32 Single 3 417.54 193 -- 0 0 124 3
64 32 Double 3 407.33 305 -- 0 0 193 3
Family Input Precision Output Precision Latency fMAX ALMs M10K M20K DSP Blocks Logic Registers
Primary Secondary
Arria V (5AGXFB3H4F40C5) Single Double 2 371.61 93 0 — 0 71 0
Double Single 2 370.64 127 0 — 0 74 1
Cyclone V (5CGXFC7D6F31C7) Single Double 2 346.14 93 0 — 0 72 1
Double Single 3 349.9 126 0 — 0 111 2
Stratix V (5SGXEA7K2F40C2) Single Double 0 — 76 — 0 0 0 0
Double Single 0 717.36 126 — 0 0 34 0
Arria 10 (10AX115H4F34I3SP) Single Double 0 — 75 — 0 0 0 0
Double Single 0 — 126 — 0 0 34 0
Level Two Title