Floating-Point IP Cores User Guide

Download PDF
ID 683750
Date 10/27/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About Floating-Point IP Cores 2. FP_ACC_CUSTOM Intel® FPGA IP or Floating Point Custom Accumulator Intel® FPGA IP Core 3. ALTFP_ADD_SUB IP Core 4. ALTFP_DIV IP Core 5. ALTFP_MULT IP Core 6. ALTFP_SQRT 7. ALTFP_EXP IP Core 8. ALTFP_INV IP Core 9. ALTFP_INV_SQRT IP Core 10. ALTFP_LOG 11. ALTFP_ATAN IP Core 12. ALTFP_SINCOS IP Core 13. ALTFP_ABS IP Core 14. ALTFP_COMPARE IP Core 15. ALTFP_CONVERT IP Core 16. FP_FUNCTIONS Intel® FPGA IP or Floating Point Functions Intel® FPGA IP Core 17. Floating-Point IP Cores User Guide Document Archives 18. Document Revision History for the Floating-Point IP Cores User Guide
1. About Floating-Point IP Cores x
1.1. List of Floating-Point IP Cores 1.2. Installing and Licensing Intel® FPGA IP Cores 1.3. Design Flow 1.4. Upgrading IP Cores 1.5. Floating-Point IP Cores General Features 1.6. IEEE-754 Standard for Floating-Point Arithmetic 1.7. Non-IEEE-754 Standard Format 1.8. Floating-Points IP Cores Output Latency 1.9. Floating-Point IP Cores Design Example Files 1.10. VHDL Component Declaration 1.11. VHDL LIBRARY-USE Declaration
1.3. Design Flow x
1.3.1. IP Catalog and Parameter Editor 1.3.2. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 1.3.3. Generating IP Cores ( Intel® Quartus® Prime Standard Edition)
1.3.1. IP Catalog and Parameter Editor x
1.3.1.1. The Parameter Editor
1.3.2. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) x
1.3.2.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
1.4. Upgrading IP Cores x
1.4.1. Migrating IP Cores to a Different Device
1.6. IEEE-754 Standard for Floating-Point Arithmetic x
1.6.1. Floating-Point Formats 1.6.2. Special Case Numbers 1.6.3. Rounding
1.6.1. Floating-Point Formats x
1.6.1.1. Single-Precision Format 1.6.1.2. Double-Precision Format 1.6.1.3. Single-Extended Precision Format
2. FP_ACC_CUSTOM Intel® FPGA IP or Floating Point Custom Accumulator Intel® FPGA IP Core x
2.1. FP_ACC_CUSTOM Intel® FPGA IP or Floating Point Custom Accumulator Intel® FPGA IP Features 2.2. FP_ACC_CUSTOM Intel® FPGA IP or Floating Point Custom Accumulator Intel® FPGA IP Output Latency 2.3. FP_ACC_CUSTOM Intel® FPGA IP Resource Utilization and Performance 2.4. FP_ACC_CUSTOM Intel® FPGA IP or Floating Point Custom Accumulator Intel® FPGA IP Signals 2.5. FP_ACC_CUSTOM Intel® FPGA IP or Floating Point Custom Accumulator Intel® FPGA IP Parameters
3. ALTFP_ADD_SUB IP Core x
3.1. ALTFP_ADD_SUB Features 3.2. ALTFP_ADD_SUB Output Latency 3.3. ALTFP_ADD_SUB Truth Table 3.4. ALTFP_ADD_SUB Resource Utilization and Performance 3.5. ALTFP_ADD_SUB Design Example: Addition of Double-Precision Format Numbers 3.6. ALTFP_ADD_SUB Signals 3.7. ALTFP_ADD_SUB Parameters
3.5. ALTFP_ADD_SUB Design Example: Addition of Double-Precision Format Numbers x
3.5.1. ALTFP_ADD_SUM Design Example: Understanding the Simulation Results
4. ALTFP_DIV IP Core x
4.1. ALTFP_DIV Features 4.2. ALTFP_DIV Output Latency 4.3. ALTFP_DIV Truth Table 4.4. ALTFP_DIV Resource Utilization and Performance 4.5. ALTFP_DIV Design Example: Division of Single-Precision 4.6. ALTFP_DIV Signals 4.7. ALTFP_DIV Parameters
4.5. ALTFP_DIV Design Example: Division of Single-Precision x
4.5.1. ALTFP_DIV Design Example: Understanding the Simulation Results
5. ALTFP_MULT IP Core x
5.1. ALTFP_MULT IP Core Features 5.2. ALTFP_MULT Output Latency 5.3. ALTFP_MULT Truth Table 5.4. ALTFP_MULT Resource Utilization and Performance 5.5. ALTFP_MULT Design Example: Multiplication of Double-Precision Format Numbers 5.6. Parameters 5.7. ALTFP_MULT Signals
5.5. ALTFP_MULT Design Example: Multiplication of Double-Precision Format Numbers x
5.5.1. ALTFP_MULT Design Example: Understanding the Simulation Waveform
6. ALTFP_SQRT x
6.1. ALTFP_SQRT Features 6.2. Output Latency 6.3. ALTFP_SQRT Truth Table 6.4. ALTFP_SQRT Resource Utilization and Performance 6.5. ALTFP_SQRT Design Example: Square Root of Single-Precision Format Numbers 6.6. ALTFP_SQRT Signals 6.7. ALTFP_SQRT Parameters
6.5. ALTFP_SQRT Design Example: Square Root of Single-Precision Format Numbers x
6.5.1. ALTFP_SQRT Design Example: Understanding the Simulation Results
7. ALTFP_EXP IP Core x
7.1. ALTFP_EXP Features 7.2. Output Latency 7.3. ALTFP_EXP Truth Table 7.4. ALTFP_EXP Resource Utilization and Performance 7.5. ALTFP_EXP Design Example: Exponential of Single-Precision Format Numbers 7.6. ALTFP_EXP Signals 7.7. ALTFP_EXP Parameters
7.5. ALTFP_EXP Design Example: Exponential of Single-Precision Format Numbers x
7.5.1. ALTFP_EXP Design Example: Understanding the Simulation Results
8. ALTFP_INV IP Core x
8.1. ALTFP_INV Features 8.2. Output Latency 8.3. ALTFP_INV Truth Table 8.4. ALTFP_INV Resource Utilization and Performance 8.5. ALTFP_INV Design Example: Inverse of Single-Precision Format Numbers 8.6. Ports 8.7. Parameters
8.5. ALTFP_INV Design Example: Inverse of Single-Precision Format Numbers x
8.5.1. ALTFP_INV Design Example: Understanding the Simulation Results
9. ALTFP_INV_SQRT IP Core x
9.1. ALTFP_INV_SQRT Features 9.2. Output Latency 9.3. ALTFP_INV_SQRT Truth Table 9.4. ALTFP_INV_SQRT Resource Utilization and Performance 9.5. ALTFP_INV_SQRT Design Example: Inverse Square Root of Single-Precision Format Numbers 9.6. Ports 9.7. Parameters
9.5. ALTFP_INV_SQRT Design Example: Inverse Square Root of Single-Precision Format Numbers x
9.5.1. ALTFP_INV_SQRT Design Example: Understanding the Simulation Results
10. ALTFP_LOG x
10.1. ALTFP_LOG Features 10.2. Output Latency 10.3. ALTFP_LOG Truth Table 10.4. ALTFP_LOG Resource Utilization and Performance 10.5. ALTFP_LOG Design Example: Natural Logarithm of Single-Precision Format Numbers 10.6. Signals 10.7. Parameters
10.5. ALTFP_LOG Design Example: Natural Logarithm of Single-Precision Format Numbers x
10.5.1. ALTFP_LOG Design Example: Understanding the Simulation Results
11. ALTFP_ATAN IP Core x
11.1. Output Latency 11.2. ALTFP_ATAN Features 11.3. ALTFP_ATAN Resource Utilization and Performance 11.4. Ports 11.5. ALTFP_ATAN Parameters
12. ALTFP_SINCOS IP Core x
12.1. ALTFP_SINCOS Features 12.2. Output Latency 12.3. ALTFP_SINCOS Resource Utilization and Performance 12.4. ALTFP_SINCOS Signals 12.5. ALTFP_SINCOS Parameters
13. ALTFP_ABS IP Core x
13.1. ALTFP_ABS Features 13.2. ALTFP_ABS Output Latency 13.3. ALTFP_ABS Resource Utilization and Performance 13.4. ALTFP_ABS Design Example: Absolute Value of Multiplication Results 13.5. ALTFP_ABS Signals 13.6. ALTFP_ABS Parameters
13.4. ALTFP_ABS Design Example: Absolute Value of Multiplication Results x
13.4.1. ALTFP_ABS Design Example: Understanding the Simulation Results
14. ALTFP_COMPARE IP Core x
14.1. ALTFP_COMPARE Features 14.2. ALTFP_COMPARE Output Latency 14.3. ALTFP_COMPARE Resource Utilization and Performance 14.4. ALTFP_COMPARE Design Example: Comparison of Single-Precision Format Numbers 14.5. ALTFP_COMPARE Signals 14.6. ALTFP_COMPARE Parameters
14.4. ALTFP_COMPARE Design Example: Comparison of Single-Precision Format Numbers x
14.4.1. ALTFP_COMPARE Design Example: Understanding the Simulation Results
15. ALTFP_CONVERT IP Core x
15.1. ALTFP_CONVERT Features 15.2. ALTFP_CONVERT Conversion Operations 15.3. ALTFP_CONVERT Output Latency 15.4. ALTFP_CONVERT Resource Utilization and Performance 15.5. ALTFP_CONVERT Design Example: Convert Double-Precision Floating-Point Format Numbers 15.6. ALTFP_CONVERT Signals 15.7. ALTFP_CONVERT Parameters
15.5. ALTFP_CONVERT Design Example: Convert Double-Precision Floating-Point Format Numbers x
15.5.1. ALTFP_CONVERT Design Example: Understanding the Simulation Results
16. FP_FUNCTIONS Intel® FPGA IP or Floating Point Functions Intel® FPGA IP Core x
16.1. FP_FUNCTIONS Intel® FPGA IP or Floating Point Functions Intel® FPGA IP Features 16.2. FP_FUNCTIONS Intel® FPGA IP or Floating Point Functions Intel® FPGA IP Output Latency 16.3. FP_FUNCTIONS Intel® FPGA IP or Floating Point Functions Intel® FPGA IP Target Frequency 16.4. FP_FUNCTIONS Intel® FPGA IP or Floating Point Functions Intel® FPGA IP Combined Target 16.5. FP_FUNCTIONS Intel® FPGA IP Resource Utilization and Performance 16.6. FP_FUNCTIONS Intel® FPGA IP Signals 16.7. FP_FUNCTIONS Intel® FPGA IP Parameters
1. About Floating-Point IP Cores
2. FP_ACC_CUSTOM Intel® FPGA IP or Floating Point Custom Accumulator Intel® FPGA IP Core
3. ALTFP_ADD_SUB IP Core
4. ALTFP_DIV IP Core
5. ALTFP_MULT IP Core
6. ALTFP_SQRT
7. ALTFP_EXP IP Core
8. ALTFP_INV IP Core
9. ALTFP_INV_SQRT IP Core
10. ALTFP_LOG
11. ALTFP_ATAN IP Core
12. ALTFP_SINCOS IP Core
13. ALTFP_ABS IP Core
14. ALTFP_COMPARE IP Core
15. ALTFP_CONVERT IP Core
16. FP_FUNCTIONS Intel® FPGA IP or Floating Point Functions Intel® FPGA IP Core
17. Floating-Point IP Cores User Guide Document Archives
18. Document Revision History for the Floating-Point IP Cores User Guide

16.7. FP_FUNCTIONS Intel® FPGA IP Parameters

These tables list the FP_FUNCTIONS Intel® FPGA IP parameters.
Table 99.  FP_FUNCTIONS Intel® FPGA IP Parameters: Functionality Tab
Parameter Values Descriptions
Function
Family
  • All
  • Arithmetic
  • Comparisons
  • Conversions
  • Exp/Log/Pow
  • Roots
  • Trigonometry
 Allows you to chose which functions to be displayed in the Function Name Parameter list. The default value is All.
Name
  • Add
  • Subtract
  • Add/Sub
  • Multiply
  • Divide
  • Reciprocal
  • Absolute
  • Scalar Product
  • Multiply Accumulate
  • Accumulate
  • Multiply Add
  • Complex Multiply
  • Sin
  • Cos
  • Tan
  • Arcsin
  • Arccos
  • Arctan
  • Arctan2
  • Exponent
  • Exponent base 2
  • Exponent base 10
  • Log
  • Log2
  • Log10
  • Log(1+x)
  • Power
  • Square Root
  • Reciprocal Square Root
  • Cube Root
  • 3D Hypotenuse
  • Minimum
  • Maximum
  • Less Than
  • Less Than or Equal
  • Equal
  • Not Equal
  • Greater Than
  • Greater Than or Equal
  • Fixed to Floating Point
  • Floating Point to Fixed
  • Floating to Floating Point
 Allows you to choose your desired function.
Note: This parameter only displays the options you have selected from the Family Parameter.
Use Select Signal — Select this option to generate a Select signal.

Use the Select signal to choose the option to use both addition and subtraction functions or either one of the functions.

Represent angle as multiple of Pi — Select this option to represent angles as multiple of Pi.
Note: Not available for Arctan2 function.
Inputs are within range -2pi to +2pi — Select this option to disable range reduction.
Note: Only available for Sin and Cos function.
Floating Point Data
Format

Single

Double

Custom

 Allows you to choose the floating point format of the data values. The default value is single.
Exponent 5 to 11 Allows you to specify the width of the exponent. This parameter is only available when the Format parameter is set to custom. The default value is 8.
Mantissa 10 to 52 Allows you to specify the width of the mantissa. This parameter is only available when the Format parameter is set to custom. The default value is 23.
Input Vector Dimension Integer Provide the desired the number of inputs to compute the vector dimension.
Input Format

Single

Double

Custom

 Allows you to choose the floating point format of the input data values. The default value is single.
Note: Only available for Floating to Floating Point function.
Input Exponent Integer Allows you to specify the width of the input exponent. This parameter is only available when the Format parameter is set to custom. The default value is 8.
Note: Only available for Floating to Floating Point function.
Input Mantissa Integer Allows you to specify the width of the mantissa. This parameter is only available when the Format parameter is set to custom. The default value is 23.
Note: Only available for Floating to Floating Point function.
Output Format

Single

Double

Custom

 Allows you to choose the floating point format of the output data values. The default value is single.
Output Exponent Integer Allows you to specify the width of the output exponent. This parameter is only available when the Format parameter is set to custom. The default value is 8.
Note: Only available for Floating to Floating Point function.
Output Mantissa Integer Allows you to specify the width of the mantissa. This parameter is only available when the Format parameter is set to custom. The default value is 23.
Note: Only available for Floating to Floating Point function.
Fixed Point Data
Width 16 to 128 The bit width of the fixed point data port. This parameter is only available when the Name parameter is set to Fixed to Floating Point. The default value is 32.
Fraction -128 to 128 The bit width of the fraction. This parameter is only available when the Name parameter is set to Fixed to Floating Point.
Sign

Signed

,

Unsigned

 Choose if the fixed point data is signed or unsigned. This parameter is only available when the Name parameter is set to Convert. The default value is signed.
Rounding
Mode
  • nearest with tie breaking to even
 The rounding mode.
Relax rounding to round up or down to reduce resource usage — Choose if the nearest rounding mode should be relaxed to faithful rounding, where the result may be rounded up or down, to reduce resource usage. Only available for arithmetic functions
Ports
Generate Enable Port — Choose if the FP_FUNCTIONS Intel® FPGA IP core should have an enable signal.
Table 100.  FP_FUNCTIONS Intel® FPGA IP Parameters: Performance Tab
Parameter Values Descriptions
Target
Goal
  • Frequency
  • Latency
  • Combined
  • Manually Specify DSP Registers
 If the Goal is the frequency, then the Target is the desired frequency in MHz. This, together with the target device family, determines the amount of pipelining. If the Goal is Combined then two Targets are displayed, one is the desired frequency in MHz, one is the target latency in cycles. When you set the Goal parameter to frequency, the default value is 200 MHz When you set the Goal parameter to latency, the default value is 2.

If the Goal is Latency, then the Target is the desired latency. The report generates the achievable latency if it can't meet target latency.

If the Goal is set to Manually Specify DSP Registers, you can manually select the register and function subblocks within the DSP IP core.

Target Any Positive Integer Specify your target frequency and latency.
Report
Latency on Arria 10 is <x> cycles — This report shows the latency of the function.
Resource Estimates:
  • Multiplies
  • LUTs
  • Memory Bits
  • Memory Blocks
— This report shows the number of multipliers, LUTs, memory bits, and memory blocks utilized by the IP core.
Check Performance — Click this to check if the design can achieve the target latency.
Note: Only available when Goal is set to Latency.
Level Two Title