Floating-Point IP Cores User Guide

Download PDF
ID 683750
Date 10/27/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About Floating-Point IP Cores 2. FP_ACC_CUSTOM Intel® FPGA IP or Floating Point Custom Accumulator Intel® FPGA IP Core 3. ALTFP_ADD_SUB IP Core 4. ALTFP_DIV IP Core 5. ALTFP_MULT IP Core 6. ALTFP_SQRT 7. ALTFP_EXP IP Core 8. ALTFP_INV IP Core 9. ALTFP_INV_SQRT IP Core 10. ALTFP_LOG 11. ALTFP_ATAN IP Core 12. ALTFP_SINCOS IP Core 13. ALTFP_ABS IP Core 14. ALTFP_COMPARE IP Core 15. ALTFP_CONVERT IP Core 16. FP_FUNCTIONS Intel® FPGA IP or Floating Point Functions Intel® FPGA IP Core 17. Floating-Point IP Cores User Guide Document Archives 18. Document Revision History for the Floating-Point IP Cores User Guide
1. About Floating-Point IP Cores x
1.1. List of Floating-Point IP Cores 1.2. Installing and Licensing Intel® FPGA IP Cores 1.3. Design Flow 1.4. Upgrading IP Cores 1.5. Floating-Point IP Cores General Features 1.6. IEEE-754 Standard for Floating-Point Arithmetic 1.7. Non-IEEE-754 Standard Format 1.8. Floating-Points IP Cores Output Latency 1.9. Floating-Point IP Cores Design Example Files 1.10. VHDL Component Declaration 1.11. VHDL LIBRARY-USE Declaration
1.3. Design Flow x
1.3.1. IP Catalog and Parameter Editor 1.3.2. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 1.3.3. Generating IP Cores ( Intel® Quartus® Prime Standard Edition)
1.3.1. IP Catalog and Parameter Editor x
1.3.1.1. The Parameter Editor
1.3.2. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) x
1.3.2.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
1.4. Upgrading IP Cores x
1.4.1. Migrating IP Cores to a Different Device
1.6. IEEE-754 Standard for Floating-Point Arithmetic x
1.6.1. Floating-Point Formats 1.6.2. Special Case Numbers 1.6.3. Rounding
1.6.1. Floating-Point Formats x
1.6.1.1. Single-Precision Format 1.6.1.2. Double-Precision Format 1.6.1.3. Single-Extended Precision Format
2. FP_ACC_CUSTOM Intel® FPGA IP or Floating Point Custom Accumulator Intel® FPGA IP Core x
2.1. FP_ACC_CUSTOM Intel® FPGA IP or Floating Point Custom Accumulator Intel® FPGA IP Features 2.2. FP_ACC_CUSTOM Intel® FPGA IP or Floating Point Custom Accumulator Intel® FPGA IP Output Latency 2.3. FP_ACC_CUSTOM Intel® FPGA IP Resource Utilization and Performance 2.4. FP_ACC_CUSTOM Intel® FPGA IP or Floating Point Custom Accumulator Intel® FPGA IP Signals 2.5. FP_ACC_CUSTOM Intel® FPGA IP or Floating Point Custom Accumulator Intel® FPGA IP Parameters
3. ALTFP_ADD_SUB IP Core x
3.1. ALTFP_ADD_SUB Features 3.2. ALTFP_ADD_SUB Output Latency 3.3. ALTFP_ADD_SUB Truth Table 3.4. ALTFP_ADD_SUB Resource Utilization and Performance 3.5. ALTFP_ADD_SUB Design Example: Addition of Double-Precision Format Numbers 3.6. ALTFP_ADD_SUB Signals 3.7. ALTFP_ADD_SUB Parameters
3.5. ALTFP_ADD_SUB Design Example: Addition of Double-Precision Format Numbers x
3.5.1. ALTFP_ADD_SUM Design Example: Understanding the Simulation Results
4. ALTFP_DIV IP Core x
4.1. ALTFP_DIV Features 4.2. ALTFP_DIV Output Latency 4.3. ALTFP_DIV Truth Table 4.4. ALTFP_DIV Resource Utilization and Performance 4.5. ALTFP_DIV Design Example: Division of Single-Precision 4.6. ALTFP_DIV Signals 4.7. ALTFP_DIV Parameters
4.5. ALTFP_DIV Design Example: Division of Single-Precision x
4.5.1. ALTFP_DIV Design Example: Understanding the Simulation Results
5. ALTFP_MULT IP Core x
5.1. ALTFP_MULT IP Core Features 5.2. ALTFP_MULT Output Latency 5.3. ALTFP_MULT Truth Table 5.4. ALTFP_MULT Resource Utilization and Performance 5.5. ALTFP_MULT Design Example: Multiplication of Double-Precision Format Numbers 5.6. Parameters 5.7. ALTFP_MULT Signals
5.5. ALTFP_MULT Design Example: Multiplication of Double-Precision Format Numbers x
5.5.1. ALTFP_MULT Design Example: Understanding the Simulation Waveform
6. ALTFP_SQRT x
6.1. ALTFP_SQRT Features 6.2. Output Latency 6.3. ALTFP_SQRT Truth Table 6.4. ALTFP_SQRT Resource Utilization and Performance 6.5. ALTFP_SQRT Design Example: Square Root of Single-Precision Format Numbers 6.6. ALTFP_SQRT Signals 6.7. ALTFP_SQRT Parameters
6.5. ALTFP_SQRT Design Example: Square Root of Single-Precision Format Numbers x
6.5.1. ALTFP_SQRT Design Example: Understanding the Simulation Results
7. ALTFP_EXP IP Core x
7.1. ALTFP_EXP Features 7.2. Output Latency 7.3. ALTFP_EXP Truth Table 7.4. ALTFP_EXP Resource Utilization and Performance 7.5. ALTFP_EXP Design Example: Exponential of Single-Precision Format Numbers 7.6. ALTFP_EXP Signals 7.7. ALTFP_EXP Parameters
7.5. ALTFP_EXP Design Example: Exponential of Single-Precision Format Numbers x
7.5.1. ALTFP_EXP Design Example: Understanding the Simulation Results
8. ALTFP_INV IP Core x
8.1. ALTFP_INV Features 8.2. Output Latency 8.3. ALTFP_INV Truth Table 8.4. ALTFP_INV Resource Utilization and Performance 8.5. ALTFP_INV Design Example: Inverse of Single-Precision Format Numbers 8.6. Ports 8.7. Parameters
8.5. ALTFP_INV Design Example: Inverse of Single-Precision Format Numbers x
8.5.1. ALTFP_INV Design Example: Understanding the Simulation Results
9. ALTFP_INV_SQRT IP Core x
9.1. ALTFP_INV_SQRT Features 9.2. Output Latency 9.3. ALTFP_INV_SQRT Truth Table 9.4. ALTFP_INV_SQRT Resource Utilization and Performance 9.5. ALTFP_INV_SQRT Design Example: Inverse Square Root of Single-Precision Format Numbers 9.6. Ports 9.7. Parameters
9.5. ALTFP_INV_SQRT Design Example: Inverse Square Root of Single-Precision Format Numbers x
9.5.1. ALTFP_INV_SQRT Design Example: Understanding the Simulation Results
10. ALTFP_LOG x
10.1. ALTFP_LOG Features 10.2. Output Latency 10.3. ALTFP_LOG Truth Table 10.4. ALTFP_LOG Resource Utilization and Performance 10.5. ALTFP_LOG Design Example: Natural Logarithm of Single-Precision Format Numbers 10.6. Signals 10.7. Parameters
10.5. ALTFP_LOG Design Example: Natural Logarithm of Single-Precision Format Numbers x
10.5.1. ALTFP_LOG Design Example: Understanding the Simulation Results
11. ALTFP_ATAN IP Core x
11.1. Output Latency 11.2. ALTFP_ATAN Features 11.3. ALTFP_ATAN Resource Utilization and Performance 11.4. Ports 11.5. ALTFP_ATAN Parameters
12. ALTFP_SINCOS IP Core x
12.1. ALTFP_SINCOS Features 12.2. Output Latency 12.3. ALTFP_SINCOS Resource Utilization and Performance 12.4. ALTFP_SINCOS Signals 12.5. ALTFP_SINCOS Parameters
13. ALTFP_ABS IP Core x
13.1. ALTFP_ABS Features 13.2. ALTFP_ABS Output Latency 13.3. ALTFP_ABS Resource Utilization and Performance 13.4. ALTFP_ABS Design Example: Absolute Value of Multiplication Results 13.5. ALTFP_ABS Signals 13.6. ALTFP_ABS Parameters
13.4. ALTFP_ABS Design Example: Absolute Value of Multiplication Results x
13.4.1. ALTFP_ABS Design Example: Understanding the Simulation Results
14. ALTFP_COMPARE IP Core x
14.1. ALTFP_COMPARE Features 14.2. ALTFP_COMPARE Output Latency 14.3. ALTFP_COMPARE Resource Utilization and Performance 14.4. ALTFP_COMPARE Design Example: Comparison of Single-Precision Format Numbers 14.5. ALTFP_COMPARE Signals 14.6. ALTFP_COMPARE Parameters
14.4. ALTFP_COMPARE Design Example: Comparison of Single-Precision Format Numbers x
14.4.1. ALTFP_COMPARE Design Example: Understanding the Simulation Results
15. ALTFP_CONVERT IP Core x
15.1. ALTFP_CONVERT Features 15.2. ALTFP_CONVERT Conversion Operations 15.3. ALTFP_CONVERT Output Latency 15.4. ALTFP_CONVERT Resource Utilization and Performance 15.5. ALTFP_CONVERT Design Example: Convert Double-Precision Floating-Point Format Numbers 15.6. ALTFP_CONVERT Signals 15.7. ALTFP_CONVERT Parameters
15.5. ALTFP_CONVERT Design Example: Convert Double-Precision Floating-Point Format Numbers x
15.5.1. ALTFP_CONVERT Design Example: Understanding the Simulation Results
16. FP_FUNCTIONS Intel® FPGA IP or Floating Point Functions Intel® FPGA IP Core x
16.1. FP_FUNCTIONS Intel® FPGA IP or Floating Point Functions Intel® FPGA IP Features 16.2. FP_FUNCTIONS Intel® FPGA IP or Floating Point Functions Intel® FPGA IP Output Latency 16.3. FP_FUNCTIONS Intel® FPGA IP or Floating Point Functions Intel® FPGA IP Target Frequency 16.4. FP_FUNCTIONS Intel® FPGA IP or Floating Point Functions Intel® FPGA IP Combined Target 16.5. FP_FUNCTIONS Intel® FPGA IP Resource Utilization and Performance 16.6. FP_FUNCTIONS Intel® FPGA IP Signals 16.7. FP_FUNCTIONS Intel® FPGA IP Parameters
1. About Floating-Point IP Cores
2. FP_ACC_CUSTOM Intel® FPGA IP or Floating Point Custom Accumulator Intel® FPGA IP Core
3. ALTFP_ADD_SUB IP Core
4. ALTFP_DIV IP Core
5. ALTFP_MULT IP Core
6. ALTFP_SQRT
7. ALTFP_EXP IP Core
8. ALTFP_INV IP Core
9. ALTFP_INV_SQRT IP Core
10. ALTFP_LOG
11. ALTFP_ATAN IP Core
12. ALTFP_SINCOS IP Core
13. ALTFP_ABS IP Core
14. ALTFP_COMPARE IP Core
15. ALTFP_CONVERT IP Core
16. FP_FUNCTIONS Intel® FPGA IP or Floating Point Functions Intel® FPGA IP Core
17. Floating-Point IP Cores User Guide Document Archives
18. Document Revision History for the Floating-Point IP Cores User Guide

14.4.1. ALTFP_COMPARE Design Example: Understanding the Simulation Results

The simulation waveform in this design example is not shown in its entirety. Run the design example files in the ModelSim* - Intel® FPGA Edition software to see the complete simulation waveforms.

This figure shows the expected simulation results in the ModelSim* - Intel® FPGA Edition software.

Figure 37. ALTFP_COMPARE Simulation Waveform

This design example implements a floating-point comparator for single-precision numbers. Both optional input ports (clk_en and aclr) and all seven output ports (ageb, aeb, agb, aneb, alb, aleb, and unordered) are enabled.

The chosen output latency is 3. Therefore, the comparison operation generates the output result 3 clock cycles later.

This table lists the inputs and corresponding outputs obtained from the simulation in the waveform.

Table 79.  Summary of Input Values and Corresponding Outputs
Time Event
0 ns, start-up dataa[] value: 619B CE11h

datab[] value: 9106 CA22h

Output value: An undefined value is seen on the result[] port, which is ignored. All values seen on the output port before the 3rd clock cycle are merely due to the behavior of the system during start-up and should be disregarded.

25 ns Output ports: ageb, aneb, and agb assert
350 ns dataa[] value: 0060 0000h

datab[] value: 0070 0000h

Both input values are denormal numbers.

375 ns Output ports: aeb, ageb, and aleb assert

Denormal inputs are not supported and are forced to zero before comparison takes place, which results in the dataa[] value being equal to datab[].

460 ns The aclr signal is set for 1 clock cycle.
495.5 ns The comparisons of subsequent data inputs are performed 3 clock cycles after the aclr signal deasserts.
Level Two Title