Low Latency 40-Gbps Ethernet IP Core User Guide

Download PDF
ID 683745
Date 3/08/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the LL 40GbE IP Core 2. Getting Started 3. Functional Description 4. Debugging the Link A. Arria 10 10GBASE-KR Registers B. Additional Information
1. About the LL 40GbE IP Core x
1.1. LL 40GbE IP Core Supported Features 1.2. IP Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Release Information
1.2. IP Core Device Family and Speed Grade Support x
1.2.1. LL 40GbE IP Core Device Family Support 1.2.2. LL 40GbE IP Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Compilation Checking 1.3.3. Hardware Testing
1.4. Performance and Resource Utilization x
1.4.1. Arria 10 Resource Utilization 1.4.2. Stratix V Resource Utilization
2. Getting Started x
2.1. Installation and Licensing for LL 40GbE IP Core for Stratix® V Devices 2.2. Installing and Licensing Intel® FPGA IP Cores 2.3. Specifying the IP Core Parameters and Options 2.4. IP Core Parameters 2.5. Files Generated for Stratix V Variations 2.6. Files Generated for Arria 10 Variations 2.7. Integrating Your IP Core in Your Design 2.8. IP Core Testbenches 2.9. Compiling the Full Design and Programming the FPGA 2.10. Initializing the IP Core
2.2. Installing and Licensing Intel® FPGA IP Cores x
2.2.1. Intel® FPGA IP Evaluation Mode
2.7. Integrating Your IP Core in Your Design x
2.7.1. Pin Assignments 2.7.2. External Transceiver Reconfiguration Controller Required in Stratix V Designs 2.7.3. Transceiver PLL Required in Arria 10 Designs 2.7.4. Handling Potential Jitter in Intel® Arria® 10 Devices 2.7.5. External Time-of-Day Module for Variations with 1588 PTP Feature 2.7.6. Clock Requirements for 40GBASE-KR4 Variations 2.7.7. External TX MAC PLL 2.7.8. Placement Settings for the LL 40GbE Core
2.8. IP Core Testbenches x
2.8.1. Testbench Behavior 2.8.2. Simulating the LL 40GbE IP Core With the Testbenches
2.8.2. Simulating the LL 40GbE IP Core With the Testbenches x
2.8.2.1. Generating the LL 40GbE Testbench 2.8.2.2. Optimizing the IP Core Simulation With the Testbenches 2.8.2.3. Optimization in the 40GBASE-KR4 Testbench 2.8.2.4. Simulating with the Modelsim Simulator 2.8.2.5. Simulating with the NCSim Simulator 2.8.2.6. Simulating with the VCS Simulator 2.8.2.7. Testbench Output Example
3. Functional Description x
3.1. High Level System Overview 3.2. LL 40GbE IP Core Functional Description 3.3. Signals 3.4. Software Interface: Registers 3.5. Ethernet Glossary
3.2. LL 40GbE IP Core Functional Description x
3.2.1. LL 40GbE IP Core TX Datapath 3.2.2. LL 40GbE IP Core TX Data Bus Interfaces 3.2.3. LL 40GbE IP Core RX Datapath 3.2.4. LL 40GbE IP Core RX Data Bus Interfaces 3.2.5. External Reconfiguration Controller 3.2.6. External Transceiver PLL 3.2.7. External TX MAC PLL 3.2.8. Congestion and Flow Control Using Pause Frames 3.2.9. Pause Control and Generation Interface 3.2.10. Pause Control Frame Filtering 3.2.11. Link Fault Signaling Interface 3.2.12. Statistics Counters Interface 3.2.13. 1588 Precision Time Protocol Interfaces 3.2.14. PHY Status Interface 3.2.15. Transceiver PHY Serial Data Interface 3.2.16. Low Latency 40GBASE-KR4 IP Core Variations 3.2.17. Control and Status Interface 3.2.18. Arria 10 Transceiver Reconfiguration Interface 3.2.19. Clocks 3.2.20. Resets
3.2.1. LL 40GbE IP Core TX Datapath x
3.2.1.1. Preamble, Start, and SFD Insertion 3.2.1.2. Address Insertion 3.2.1.3. Length/Type Field Processing 3.2.1.4. Frame Padding 3.2.1.5. Frame Check Sequence (CRC-32) Insertion 3.2.1.6. Inter-Packet Gap Generation and Insertion 3.2.1.7. Error Insertion Test and Debug Feature
3.2.2. LL 40GbE IP Core TX Data Bus Interfaces x
3.2.2.1. LL 40GbE IP Core User Interface Data Bus 3.2.2.2. LL 40GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface) 3.2.2.3. LL 40GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface) 3.2.2.4. Bus Quantization Effects With Adapters 3.2.2.5. User Interface to Ethernet Transmission
3.2.2.5. User Interface to Ethernet Transmission x
3.2.2.5.1. Order of Transmission
3.2.3. LL 40GbE IP Core RX Datapath x
3.2.3.1. LL 40GbE IP Core RX Filtering 3.2.3.2. LL 40GbE IP Core Preamble Processing 3.2.3.3. IP Core Strict SFD Checking 3.2.3.4. LL 40GbE IP Core FCS (CRC-32) Removal 3.2.3.5. LL 40GbE IP Core CRC Checking 3.2.3.6. LL 40GbE IP Core Malformed Packet Handling 3.2.3.7. RX CRC Forwarding 3.2.3.8. Inter-Packet Gap 3.2.3.9. Pause Ignore 3.2.3.10. Control Frame Identification
3.2.4. LL 40GbE IP Core RX Data Bus Interfaces x
3.2.4.1. LL 40GbE IP Core User Interface Data Bus 3.2.4.2. LL 40GbE IP Core RX Data Bus with Adapters (Avalon-ST Interface) 3.2.4.3. LL 40GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface)
3.2.8. Congestion and Flow Control Using Pause Frames x
3.2.8.1. Conditions Triggering XOFF Frame Transmission 3.2.8.2. Conditions Triggering XON Frame Transmission
3.2.12. Statistics Counters Interface x
3.2.12.1. OctetOK Count Interface
3.2.13. 1588 Precision Time Protocol Interfaces x
3.2.13.1. Implementing a 1588 System That Includes a LL 40GbE Core 3.2.13.2. PTP Receive Functionality 3.2.13.3. PTP Transmit Functionality 3.2.13.4. External Time-of-Day Module for 1588 PTP Variations 3.2.13.5. PTP Timestamp and TOD Formats 3.2.13.6. 1588 PTP Interface Signals
3.3. Signals x
3.3.1. LL 40GbE IP Core Signals
3.4. Software Interface: Registers x
3.4.1. LL 40GbE IP Core Registers 3.4.2. LL 40GbE Hardware Design Example Registers
3.4.1. LL 40GbE IP Core Registers x
3.4.1.1. PHY Registers 3.4.1.2. Link Fault Signaling Registers 3.4.1.3. LL 40GBASE-KR4 Registers 3.4.1.4. LL 40GbE IP Core MAC Configuration Registers 3.4.1.5. Pause Registers 3.4.1.6. TX Statistics Registers 3.4.1.7. RX Statistics Registers 3.4.1.8. 1588 PTP Registers
3.4.2. LL 40GbE Hardware Design Example Registers x
3.4.2.1. Packet Client Registers
4. Debugging the Link x
4.1. Creating a Signal Tap Debug File to Match Your Design Hierarchy
A. Arria 10 10GBASE-KR Registers x
A.1. 10GBASE-KR PHY Register Definitions
B. Additional Information x
B.1. LL 40GbE IP Core User Guide Archives B.2. LL 40GbE IP Core User Guide Revision History
1. About the LL 40GbE IP Core
2. Getting Started
3. Functional Description
4. Debugging the Link
A. Arria 10 10GBASE-KR Registers
B. Additional Information

2.8.2.1. Generating the LL 40GbE Testbench

A single procedure generates the testbench and example project (for Stratix V variations) or the testbench, compilation-only design example, and hardware design example (for Arria 10 variations). The procedure varies depending on your target device. To generate these demonstration aids:

  1. Follow the steps in Specifying the IP Core Parameters and Options to parameterize your IP core.
  2. If your IP core variation targets a Stratix V device, go to step 4.
  3. If your IP core variation targets an Arria 10 device, in the LL 40GbE parameter editor:
    • On the Example Design tab, select Simulation, Synthesis, or both to specify whether you want to generate the simulation-only testbench, the compilation-only and hardware design examples, or all three options.
    • Click the Generate Example Design button to generate these options for the IP core variation you intend to generate.
    Tip: You are prompted to locate the new testbench and example project in the directory <working directory>/alt_eth_ultra_40_0_example_design . You can accept the default path or modify the path to the new testbench and example project.
  4. Generate the IP core by clicking Generate HDL for Arria 10 variations or Generate for Stratix V variations.
    Note: If your IP core variation targets a Stratix V device, when prompted at the start of generation, you must turn on Generate example design. Turning on Generate example design is the only process that generates a functional testbench and a functional example project for Stratix V variations.

    When the IP core is generated in <working directory>, the testbench and example projects are generated in different locations depending on the device family your IP core variation targets.

    • For Stratix V variations, the testbench and example project are generated in <working directory>/<IP core variation>_example_design/alt_eth_ultra.
    • For Arria 10 variations, the testench and the compilation-only and hardware design examples are generated in the directory you specify in Step 3. If you do not modify the location text at the prompt, they are generated in <working directory>/alt_eth_ultra_40_0_example_design .

The directory with the testbench and design example has four subdirectories for Arria 10 variations and three subdirectories for Stratix V variations:

  • example_testbench
  • compilation_test_design
  • hardware_test_design
  • ex_40g , for Arria 10 variations only

The ex_40g directory contains a copy of the IP core variation. The testbench and design examples (compilation-only and hardware design example) for your Arria 10 IP core variation connect to the copy in this directory rather than to the copy you generate in <working directory>.

Related Information
Level Two Title