Low Latency 40-Gbps Ethernet IP Core User Guide

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ID 683745
Date 3/08/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the LL 40GbE IP Core 2. Getting Started 3. Functional Description 4. Debugging the Link A. Arria 10 10GBASE-KR Registers B. Additional Information
1. About the LL 40GbE IP Core x
1.1. LL 40GbE IP Core Supported Features 1.2. IP Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Release Information
1.2. IP Core Device Family and Speed Grade Support x
1.2.1. LL 40GbE IP Core Device Family Support 1.2.2. LL 40GbE IP Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Compilation Checking 1.3.3. Hardware Testing
1.4. Performance and Resource Utilization x
1.4.1. Arria 10 Resource Utilization 1.4.2. Stratix V Resource Utilization
2. Getting Started x
2.1. Installation and Licensing for LL 40GbE IP Core for Stratix® V Devices 2.2. Installing and Licensing Intel® FPGA IP Cores 2.3. Specifying the IP Core Parameters and Options 2.4. IP Core Parameters 2.5. Files Generated for Stratix V Variations 2.6. Files Generated for Arria 10 Variations 2.7. Integrating Your IP Core in Your Design 2.8. IP Core Testbenches 2.9. Compiling the Full Design and Programming the FPGA 2.10. Initializing the IP Core
2.2. Installing and Licensing Intel® FPGA IP Cores x
2.2.1. Intel® FPGA IP Evaluation Mode
2.7. Integrating Your IP Core in Your Design x
2.7.1. Pin Assignments 2.7.2. External Transceiver Reconfiguration Controller Required in Stratix V Designs 2.7.3. Transceiver PLL Required in Arria 10 Designs 2.7.4. Handling Potential Jitter in Intel® Arria® 10 Devices 2.7.5. External Time-of-Day Module for Variations with 1588 PTP Feature 2.7.6. Clock Requirements for 40GBASE-KR4 Variations 2.7.7. External TX MAC PLL 2.7.8. Placement Settings for the LL 40GbE Core
2.8. IP Core Testbenches x
2.8.1. Testbench Behavior 2.8.2. Simulating the LL 40GbE IP Core With the Testbenches
2.8.2. Simulating the LL 40GbE IP Core With the Testbenches x
2.8.2.1. Generating the LL 40GbE Testbench 2.8.2.2. Optimizing the IP Core Simulation With the Testbenches 2.8.2.3. Optimization in the 40GBASE-KR4 Testbench 2.8.2.4. Simulating with the Modelsim Simulator 2.8.2.5. Simulating with the NCSim Simulator 2.8.2.6. Simulating with the VCS Simulator 2.8.2.7. Testbench Output Example
3. Functional Description x
3.1. High Level System Overview 3.2. LL 40GbE IP Core Functional Description 3.3. Signals 3.4. Software Interface: Registers 3.5. Ethernet Glossary
3.2. LL 40GbE IP Core Functional Description x
3.2.1. LL 40GbE IP Core TX Datapath 3.2.2. LL 40GbE IP Core TX Data Bus Interfaces 3.2.3. LL 40GbE IP Core RX Datapath 3.2.4. LL 40GbE IP Core RX Data Bus Interfaces 3.2.5. External Reconfiguration Controller 3.2.6. External Transceiver PLL 3.2.7. External TX MAC PLL 3.2.8. Congestion and Flow Control Using Pause Frames 3.2.9. Pause Control and Generation Interface 3.2.10. Pause Control Frame Filtering 3.2.11. Link Fault Signaling Interface 3.2.12. Statistics Counters Interface 3.2.13. 1588 Precision Time Protocol Interfaces 3.2.14. PHY Status Interface 3.2.15. Transceiver PHY Serial Data Interface 3.2.16. Low Latency 40GBASE-KR4 IP Core Variations 3.2.17. Control and Status Interface 3.2.18. Arria 10 Transceiver Reconfiguration Interface 3.2.19. Clocks 3.2.20. Resets
3.2.1. LL 40GbE IP Core TX Datapath x
3.2.1.1. Preamble, Start, and SFD Insertion 3.2.1.2. Address Insertion 3.2.1.3. Length/Type Field Processing 3.2.1.4. Frame Padding 3.2.1.5. Frame Check Sequence (CRC-32) Insertion 3.2.1.6. Inter-Packet Gap Generation and Insertion 3.2.1.7. Error Insertion Test and Debug Feature
3.2.2. LL 40GbE IP Core TX Data Bus Interfaces x
3.2.2.1. LL 40GbE IP Core User Interface Data Bus 3.2.2.2. LL 40GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface) 3.2.2.3. LL 40GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface) 3.2.2.4. Bus Quantization Effects With Adapters 3.2.2.5. User Interface to Ethernet Transmission
3.2.2.5. User Interface to Ethernet Transmission x
3.2.2.5.1. Order of Transmission
3.2.3. LL 40GbE IP Core RX Datapath x
3.2.3.1. LL 40GbE IP Core RX Filtering 3.2.3.2. LL 40GbE IP Core Preamble Processing 3.2.3.3. IP Core Strict SFD Checking 3.2.3.4. LL 40GbE IP Core FCS (CRC-32) Removal 3.2.3.5. LL 40GbE IP Core CRC Checking 3.2.3.6. LL 40GbE IP Core Malformed Packet Handling 3.2.3.7. RX CRC Forwarding 3.2.3.8. Inter-Packet Gap 3.2.3.9. Pause Ignore 3.2.3.10. Control Frame Identification
3.2.4. LL 40GbE IP Core RX Data Bus Interfaces x
3.2.4.1. LL 40GbE IP Core User Interface Data Bus 3.2.4.2. LL 40GbE IP Core RX Data Bus with Adapters (Avalon-ST Interface) 3.2.4.3. LL 40GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface)
3.2.8. Congestion and Flow Control Using Pause Frames x
3.2.8.1. Conditions Triggering XOFF Frame Transmission 3.2.8.2. Conditions Triggering XON Frame Transmission
3.2.12. Statistics Counters Interface x
3.2.12.1. OctetOK Count Interface
3.2.13. 1588 Precision Time Protocol Interfaces x
3.2.13.1. Implementing a 1588 System That Includes a LL 40GbE Core 3.2.13.2. PTP Receive Functionality 3.2.13.3. PTP Transmit Functionality 3.2.13.4. External Time-of-Day Module for 1588 PTP Variations 3.2.13.5. PTP Timestamp and TOD Formats 3.2.13.6. 1588 PTP Interface Signals
3.3. Signals x
3.3.1. LL 40GbE IP Core Signals
3.4. Software Interface: Registers x
3.4.1. LL 40GbE IP Core Registers 3.4.2. LL 40GbE Hardware Design Example Registers
3.4.1. LL 40GbE IP Core Registers x
3.4.1.1. PHY Registers 3.4.1.2. Link Fault Signaling Registers 3.4.1.3. LL 40GBASE-KR4 Registers 3.4.1.4. LL 40GbE IP Core MAC Configuration Registers 3.4.1.5. Pause Registers 3.4.1.6. TX Statistics Registers 3.4.1.7. RX Statistics Registers 3.4.1.8. 1588 PTP Registers
3.4.2. LL 40GbE Hardware Design Example Registers x
3.4.2.1. Packet Client Registers
4. Debugging the Link x
4.1. Creating a Signal Tap Debug File to Match Your Design Hierarchy
A. Arria 10 10GBASE-KR Registers x
A.1. 10GBASE-KR PHY Register Definitions
B. Additional Information x
B.1. LL 40GbE IP Core User Guide Archives B.2. LL 40GbE IP Core User Guide Revision History
1. About the LL 40GbE IP Core
2. Getting Started
3. Functional Description
4. Debugging the Link
A. Arria 10 10GBASE-KR Registers
B. Additional Information

3.3.1. LL 40GbE IP Core Signals

The signals of the LL 40GbE IP core are described in the following formats:

  • The figure identifies the IP core interfaces.
  • Tables list the signals and the interfaces to which they belong.
  • Links guide you to descriptions for the individual signals, by interface. The links appear in Related Links.
Figure 36. Top-Level Signals of the LL 40GbE IP Core In the figure, <N> is the number of priority flow control queues. (<N> = 1 for IP cores configured with standard flow control or with no flow control, and <N> = the value of the relevant parameter for IP cores configured with priority-based flow control). In the 1588 PTP signals, <W> is the width of the fingerprint.
Table 32.   LL 40GbE IP Core Signals

Signal Name

Direction

Interface

clk_ref

Input

Clocks

clk_rx_recover Output Clocks

This signal is only available if you turn on Enable SyncE in the parameter editor.

reset_async

Input

Reset

tx_serial[3:0]

Output

Transceiver PHY serial data interface

rx_pcs_ready

Output

PHY status

tx_lanes_stable Output
clk_txmac_in Input

Clocks

Interface to external TX MAC PLL

This signal is only available if you turn on Enable external TX MAC PLL in the parameter editor.

clk_txmac

Output

Clocks

TX client interface

l4_tx_data[255:0]

Input

Avalon-ST TX client interface

Each IP core instance has Avalon-ST TX and RX client interfaces, or custom streaming TX and RX client interfaces.

l4_tx_empty[4:0]

Input

l4_tx_startofpacket

Input

l4_tx_endofpacket

Input

l4_tx_ready

Output

l4_tx_valid

Input

l4_tx_error

Input

din[127:0]

Input

Custom streaming TX client interface

Each IP core instance has Avalon-ST TX and RX client interfaces, or custom streaming TX and RX client interfaces.

din_sop[1:0]

Input

din_eop[1:0]

Input

din_eop_empty[5:0]

Input

din_idle[1:0]

Input

din_req

Output

tx_error[1:0]

Input
clk_rxmac

Output

Clocks

RX client interface

l4_rx_data[255:0]

Output

Avalon-ST RX client interface

Each IP core instance has Avalon-ST TX and RX client interfaces, or custom streaming TX and RX client interfaces.

l4_rx_empty[4:0]

Output

l4_rx_startofpacket

Output

l4_rx_endofpacket

Output

l4_rx_error[5:0]

Output

l4_rx_valid

Output

l4_rx_fcs_valid

Output

l4_rx_fcs_error

Output

l4_rx_status[2:0]

Output

dout_d[127:0]

Output

Custom streaming RX client interface

Each IP core instance has Avalon-ST TX and RX client interfaces, or custom streaming TX and RX client interfaces.

dout_c[15:0]

Output

dout_sop[1:0]

Output

dout_eop[1:0]

Output

dout_eop_empty[5:0]

Output

dout_idle[1:0]

Output
rx_error[5:0] Output
rx_fcs_error

Output

rx_fcs_valid

Output

rx_status[2:0] Output
dout_valid

Output

pause_insert_tx[<N>-1:0]

Input

Pause control and generation interface

pause_receive_rx[<N>-1:0]

Output

remote_fault_status

Output

Link fault signaling interface

These signals are available only in IP core variations that include the link fault signaling module.

local_fault_status

Output

unidirectional_en Output

Link fault signaling interface, Clause 66 status

These signals are available only in IP core variations that include the link fault signaling module.

link_fault_gen_en Output
tx_inc_64

Output

TX statistics counter increment vectors

These signals are available whether or not your IP core includes TX statistics counters.

tx_inc_127

Output

tx_inc_255

Output

tx_inc_511

Output

tx_inc_1023

Output

tx_inc_1518

Output

tx_inc_max

Output

tx_inc_over

Output

tx_inc_mcast_data_err

Output

tx_inc_mcast_data_ok

Output

tx_inc_bcast_data_err

Output

tx_inc_bcast_data_ok

Output

tx_inc_ucast_data_err

Output

tx_inc_ucast_data_ok

Output

tx_inc_mcast_ctrl

Output

tx_inc_bcast_ctrl

Output

tx_inc_ucast_ctrl

Output

tx_inc_pause

Output

tx_inc_fcs_err

Output

tx_inc_fragment

Output

tx_inc_jabber

Output

tx_inc_sizeok_fcserr

Output

rx_inc_runt

Output

RX statistics counter increment vectors

These signals are available whether or not your IP core includes RX statistics counters.

rx_inc_64

Output

rx_inc_127

Output

rx_inc_255

Output

rx_inc_511

Output

rx_inc_1023

Output

rx_inc_1518

Output

rx_inc_max

Output

rx_inc_over

Output

rx_inc_mcast_data_err

Output

rx_inc_mcast_data_ok

Output

rx_inc_bcast_data_err

Output

rx_inc_bcast_data_ok

Output

rx_inc_ucast_data_err

Output

rx_inc_ucast_data_ok

Output

rx_inc_mcast_ctrl

Output

rx_inc_bcast_ctrl

Output

rx_inc_ucast_ctrl

Output

rx_inc_pause

Output

rx_inc_fcs_err

Output

rx_inc_fragment

Output

rx_inc_jabber

Output

rx_inc_sizeok_fcserr

Output

rx_inc_pause_ctrl_err

Output

rx_inc_mcast_ctrl_err

Output

rx_inc_bcast_ctrl_err

Output

rx_inc_ucast_ctrl_err

Output

tx_inc_octetsOK[15:0] Output

OctetOK Count interface
tx_inc_octetsOK_valid Output
rx_inc_octetsOK[15:0] Output
rx_inc_octetsOK_valid Output
clk_status

Input

Clocks

Control and status interface

reset_status

Input

Resets

Control and status interface

status_addr[15:0]

Input

Control and status interface

status_read

Input

status_write

Input

status_writedata[31:0]

Input

status_readdata[31:0]

Output

status_readdata_valid

Output

status_waitrequest

Output

status_read_timeout

Output

tx_time_of_day_96b_data[95:0] Input

1588 PTP interface

These signals are available only if 1588 PTP functionality is included in the IP core.

tx_time_of_day_64b_data[63:0] Input
rx_time_of_day_96b_data[95:0] Input
rx_time_of_day_64b_data[63:0] Input
tx_etstamp_ins_ctrl_timestamp_insert Input
tx_etstamp_ins_ctrl_residence_time_update Input
tx_etstamp_ins_ctrl_ingress_timestamp_96b[95:0]

Input

tx_etstamp_ins_ctrl_ingress_timestamp_64b[63:0]

Input

tx_etstamp_ins_ctrl_timestamp_format

Input

tx_etstamp_ins_ctrl_residence_time_calc_format

Input
tx_etstamp_ins_ctrl_offset_timestamp[15:0]

Input
tx_etstamp_ins_ctrl_offset_correction_field[15:0]

Input
tx_etstamp_ins_ctrl_checksum_zero

Input

tx_etstamp_ins_ctrl_offset_checksum_field[15:0]

Input

tx_etstamp_ins_ctrl_checksum_correct

Input

tx_etstamp_ins_ctrl_offset_checksum_correction[15:0]

Input

tx_egress_asymmetry_update

Input

tx_egress_timestamp_request_valid

Input

tx_egress_timestamp_96b_data[95:0]

Output

tx_egress_timestamp_96b_valid

Output

tx_egress_timestamp_64b_data[63:0]

Output

tx_egress_timestamp_64b_valid

Output

tx_egress_timestamp_request_fingerprint[(W–1):0]

Input

tx_egress_timestamp_96b_fingerprint[(W–1):0]

Output

tx_egress_timestamp_64b_fingerprint[(W–1):0]

Output

rx_ingress_timestamp_96b_data[95:0]

Output

rx_ingress_timestamp_96b_valid Output
rx_ingress_timestamp_64b_data[63:0]

Output

rx_ingress_timestamp_64b_valid

Output

reconfig_to_xcvr[559:0]

Input

Interface to Stratix V reconfiguration controller

These signals are available in Stratix V devices only.

reconfig_from_xcvr[367:0]

Output

reconfig_busy

Input

reconfig_clk

Input

Clocks

Arria 10 Native PHY IP core reconfiguration interface

This signal is available in Arria 10 devices only.

reconfig_reset

Input

Resets

Arria 10 Native PHY IP core reconfiguration interface

This signal is available in Arria 10 devices only.

reconfig_address [11:0]

Input

Arria 10 Native PHY IP core reconfiguration interface

These signals are available in Arria 10 devices only.

reconfig_read

Input

reconfig_write

Input

reconfig_writedata[31:0]

Input

reconfig_readdata[31:0]

Output

reconfig_waitrequest

Output

pll_locked

Input

External transceiver PLL interface. These signals are available in Arria 10 devices only.

tx_serial_clk[3:0]

Input

Related Information
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