Intel® Stratix® 10 Device Design Guidelines

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ID 683738
Date 8/24/2022
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Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 Device Design Guidelines
Intel® Stratix® 10 Device Design Guidelines x
Design Flow System Specification Device Selection Early System and Board Planning Pin Connection Considerations for Board Design I/O and Clock Planning Security Considerations Design Entry Design Implementation, Analysis, Optimization, and Verification Document Revision History for Intel® Stratix® 10 Device Design Guidelines
System Specification x
Design Specifications IP Selection Platform Designer
Device Selection x
Device Variant PLLs and Clock Routing Logic, Memory, and Multiplier Density I/O Pin Count, LVDS Channels, and Package Offering Speed Grade Vertical Device Migration
Early System and Board Planning x
Power and Thermal Estimation Thermal Management and Design Temperature Sensing for Thermal Management Voltage Sensor Planning for Device Configuration Planning for On-Chip Debugging
Planning for Device Configuration x
Device Power Cycling and Reconfiguration Configuration Scheme Selection Configuration Features Intel® Quartus® Prime Configuration Settings
Configuration Scheme Selection x
Serial Configuration Devices Download Cables
Intel® Quartus® Prime Configuration Settings x
Optional Configuration Pins Dual Purpose Configuration Pins
Planning for On-Chip Debugging x
On-Chip Debugging Tools Planning Guidelines for Debugging Tools
Pin Connection Considerations for Board Design x
Device Power-Up Power Pin Connections and Power Supplies Configuration Pin Connections Board-Related Intel® Quartus® Prime Settings Signal Integrity Considerations Board-Level Simulation and Advanced I/O Timing Analysis
Power Pin Connections and Power Supplies x
Decoupling Capacitors PLL Board Design Guidelines Transceiver Board Design Guidelines
Configuration Pin Connections x
Configuration Pin Voltage Level Clock Trace Signal Integrity JTAG Pins MSEL Configuration Mode Pins Other Configuration Pins
JTAG Pins x
JTAG Pin Connections Download Cable Operating Voltage JTAG Signal Buffering
Board-Related Intel® Quartus® Prime Settings x
Unused Pins
Signal Integrity Considerations x
High-Speed Board Design Voltage Reference Pins Simultaneous Switching Noise I/O Termination
I/O and Clock Planning x
Making FPGA Pin Assignments Early Pin Planning and I/O Assignment Analysis I/O Features and Pin Connections Clock and PLL Selection PLL Feature Guidelines Clock Control Features I/O Simultaneous Switching Noise
I/O Features and Pin Connections x
I/O Signaling Type Selectable Standards and Flexible I/O Banks Memory Interfaces Dual-Purpose and Special Pin Connections Intel® Stratix® 10 I/O Features
PLL Feature Guidelines x
Clock Feedback Mode Clock Outputs
Design Entry x
Design Recommendations Using IP Cores Reconfiguration Recommended HDL Coding Styles
Design Implementation, Analysis, Optimization, and Verification x
Selecting a Synthesis Tool Device Resource Utilization Reports Intel® Quartus® Prime Messages Timing Constraints and Analysis Area and Timing Optimization Preserving Performance and Reducing Compilation Time Designing with Intel® Hyperflex™ Simulation Power Analysis Power Optimization
Timing Constraints and Analysis x
Recommended Timing Optimization and Analysis Assignments
Power Optimization x
Device and Design Power Optimization Techniques Intel® Quartus® Prime Power Optimization Techniques
Device and Design Power Optimization Techniques x
Device Speed Grade Clock Power Management Memory Power Reduction I/O Power Guidelines
Intel® Quartus® Prime Power Optimization Techniques x
Power Optimization Advisor
Intel® Stratix® 10 Device Design Guidelines

I/O Simultaneous Switching Noise

Table 59.  I/O Simultaneous Switching Noise Checklist
Number Done? Checklist Item
1   Reduce the number of pins that switch the voltage level at exactly the same time whenever possible.
2   Use differential I/O standards and lower-voltage standards for high-switching I/Os.
3   Use lower drive strengths for high-switching I/Os. The default drive strength setting might be higher than your design requires.
4   Reduce the number of simultaneously switching output pins within each bank. Spread output pins across multiple banks if possible.
5   Spread switching I/Os evenly throughout the bank to reduce the number of aggressors in a given area to reduce SSN (when bank usage is substantially below 100%).
6   Separate simultaneously switching pins from input pins that are susceptible to SSN.
7   Place important clock and asynchronous control signals near ground signals and away from large switching buses.
8   Avoid using I/O pins one or two pins away from PLL power supply pins for high-switching or high-drive strength pins.
9   Use staggered output delays to shift the output signals through time, or use adjustable slew rate settings.
10   Limit the number of unterminated SSO pins within the I/O bank where the PLL output clock resides to achieve the Intel® Stratix® 10 I/O PLL clock output jitter performance specification.

SSN is a concern when too many I/Os (in close proximity) change voltage levels at the same time. Plan the I/O and clock connections according to the recommendations.

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