Intel® Stratix® 10 Device Design Guidelines

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ID 683738
Date 8/24/2022
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Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 Device Design Guidelines
Intel® Stratix® 10 Device Design Guidelines x
Design Flow System Specification Device Selection Early System and Board Planning Pin Connection Considerations for Board Design I/O and Clock Planning Security Considerations Design Entry Design Implementation, Analysis, Optimization, and Verification Document Revision History for Intel® Stratix® 10 Device Design Guidelines
System Specification x
Design Specifications IP Selection Platform Designer
Device Selection x
Device Variant PLLs and Clock Routing Logic, Memory, and Multiplier Density I/O Pin Count, LVDS Channels, and Package Offering Speed Grade Vertical Device Migration
Early System and Board Planning x
Power and Thermal Estimation Thermal Management and Design Temperature Sensing for Thermal Management Voltage Sensor Planning for Device Configuration Planning for On-Chip Debugging
Planning for Device Configuration x
Device Power Cycling and Reconfiguration Configuration Scheme Selection Configuration Features Intel® Quartus® Prime Configuration Settings
Configuration Scheme Selection x
Serial Configuration Devices Download Cables
Intel® Quartus® Prime Configuration Settings x
Optional Configuration Pins Dual Purpose Configuration Pins
Planning for On-Chip Debugging x
On-Chip Debugging Tools Planning Guidelines for Debugging Tools
Pin Connection Considerations for Board Design x
Device Power-Up Power Pin Connections and Power Supplies Configuration Pin Connections Board-Related Intel® Quartus® Prime Settings Signal Integrity Considerations Board-Level Simulation and Advanced I/O Timing Analysis
Power Pin Connections and Power Supplies x
Decoupling Capacitors PLL Board Design Guidelines Transceiver Board Design Guidelines
Configuration Pin Connections x
Configuration Pin Voltage Level Clock Trace Signal Integrity JTAG Pins MSEL Configuration Mode Pins Other Configuration Pins
JTAG Pins x
JTAG Pin Connections Download Cable Operating Voltage JTAG Signal Buffering
Board-Related Intel® Quartus® Prime Settings x
Unused Pins
Signal Integrity Considerations x
High-Speed Board Design Voltage Reference Pins Simultaneous Switching Noise I/O Termination
I/O and Clock Planning x
Making FPGA Pin Assignments Early Pin Planning and I/O Assignment Analysis I/O Features and Pin Connections Clock and PLL Selection PLL Feature Guidelines Clock Control Features I/O Simultaneous Switching Noise
I/O Features and Pin Connections x
I/O Signaling Type Selectable Standards and Flexible I/O Banks Memory Interfaces Dual-Purpose and Special Pin Connections Intel® Stratix® 10 I/O Features
PLL Feature Guidelines x
Clock Feedback Mode Clock Outputs
Design Entry x
Design Recommendations Using IP Cores Reconfiguration Recommended HDL Coding Styles
Design Implementation, Analysis, Optimization, and Verification x
Selecting a Synthesis Tool Device Resource Utilization Reports Intel® Quartus® Prime Messages Timing Constraints and Analysis Area and Timing Optimization Preserving Performance and Reducing Compilation Time Designing with Intel® Hyperflex™ Simulation Power Analysis Power Optimization
Timing Constraints and Analysis x
Recommended Timing Optimization and Analysis Assignments
Power Optimization x
Device and Design Power Optimization Techniques Intel® Quartus® Prime Power Optimization Techniques
Device and Design Power Optimization Techniques x
Device Speed Grade Clock Power Management Memory Power Reduction I/O Power Guidelines
Intel® Quartus® Prime Power Optimization Techniques x
Power Optimization Advisor
Intel® Stratix® 10 Device Design Guidelines

Planning for Device Configuration

Table 15.  Planning for Device Configuration Checklist
Number Done? Checklist Item
1   Consider whether you require multiple configuration schemes.
2   To avoid configuration failure, follow the configuration guidelines and additional clock requirements if your design is using PCIe, transceiver channels, HPS EMIF, High Bandwidth Memory (HBM2) IP core, or SmartVID. Refer to the Intel® Stratix® 10 Configuration User Guide and Intel® Stratix® 10 Power Management User Guide for the guidelines.
3   Intel strongly recommends using the Intel® Stratix® 10 Reset Release IP in your design to provide a known initialized state for your logic to begin operation. The Reset Release IP is available in the Intel® Quartus® Prime software version 19.1 and later. Refer to the Intel® Stratix® 10 Configuration User Guide for the guidelines.
4   Each die in the Intel® Stratix® 10 GX 10M devices has its own configuration pins. Configure each die separately by using the dedicated configuration bit stream or .sof file. The device cannot be configured using a single .sof file because each die has a unique JTAG ID.
5   Ensure nCONFIG is connected in following manner:
  • If you are using AS ×4 configuration, connect nCONFIG to VCCIO_SDM through an external 10 kΩ pull-up resistor. If the nCONFIG pin is connected and controlled by a host, the host must drive the nCONFIG to a known state. However, Intel recommends connecting nCONFIG to an external 10 kΩ pull-up resistor to VCCIO_SDM so that the FPGA can be configured directly from Quad SPI flash when the device is powered up.
  • If you are using Avalon® -ST configuration scheme, drive the nCONFIG with the host to a known a state. Connecting nCONFIG to an external 10 kΩ pull-up resistor to VCCIO_SDM is optional.
  • When you use a host to drive nCONFIG regardless of the configuration scheme, the host must monitor nSTATUS appropriately as described in the Intel® Stratix® 10 Device Family Pin Connection Guidelines and Intel® Stratix® 10 Configuration User Guide to enable reliable configuration.
6   Ensure that nCONFIG is not directly driven by FPGA, HPS I/Os, or any component that has dependency on FPGA or HPS I/Os.
7   For Intel® Stratix® 10 devices, do not reset the Quad SPI flash when used as the configuration device and data storage device with FPGA. Resetting the Quad SPI flash during the FPGA configuration and reconfiguration, or during the READ/WRITE/ERASE operations of the Quad SPI, causes undefined behavior for Quad SPI flash and the FPGA. To recover from the unresponsive behavior, you must power cycle your device. To reset the Quad SPI flash via the external host, you must first complete the FPGA configuration and reconfiguration, or a Quad SPI operation, and only then toggle the reset. The Quad SPI operation is complete when the exclusive access to the Quad SPI flash is closed by issuing the QSPI_CLOSE command via the Mailbox Client Intel® FPGA IP or CLOSE command via the Serial Flash Mailbox Client Intel® FPGA IP.

Intel® Stratix® 10 devices are based on SRAM cells. You must download configuration data to the Intel® Stratix® 10 device each time the device powers up, because SRAM is volatile. Consider whether you require multiple configuration schemes, such as one for debugging or testing and another for the production environment.

Choosing the device configuration method early allows system and board designers to determine what companion devices, if any, are required for the system. Your board layout also depends on the configuration method you plan to use for the programmable device, because different schemes require different connections.

In addition, Intel® Stratix® 10 devices offer advanced configuration features, depending on your configuration scheme. Intel® Stratix® 10 devices also include optional configuration pins and a reconfiguration option that you should choose early in the design process (and set up in the Intel® Quartus® Prime software), so you have all the information required for your board and system design.


Section Content
Device Power Cycling and Reconfiguration
Configuration Scheme Selection
Configuration Features
Intel Quartus Prime Configuration Settings

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