Intel® Stratix® 10 Device Design Guidelines

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ID 683738
Date 8/24/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 Device Design Guidelines
Intel® Stratix® 10 Device Design Guidelines x
Design Flow System Specification Device Selection Early System and Board Planning Pin Connection Considerations for Board Design I/O and Clock Planning Security Considerations Design Entry Design Implementation, Analysis, Optimization, and Verification Document Revision History for Intel® Stratix® 10 Device Design Guidelines
System Specification x
Design Specifications IP Selection Platform Designer
Device Selection x
Device Variant PLLs and Clock Routing Logic, Memory, and Multiplier Density I/O Pin Count, LVDS Channels, and Package Offering Speed Grade Vertical Device Migration
Early System and Board Planning x
Power and Thermal Estimation Thermal Management and Design Temperature Sensing for Thermal Management Voltage Sensor Planning for Device Configuration Planning for On-Chip Debugging
Planning for Device Configuration x
Device Power Cycling and Reconfiguration Configuration Scheme Selection Configuration Features Intel® Quartus® Prime Configuration Settings
Configuration Scheme Selection x
Serial Configuration Devices Download Cables
Intel® Quartus® Prime Configuration Settings x
Optional Configuration Pins Dual Purpose Configuration Pins
Planning for On-Chip Debugging x
On-Chip Debugging Tools Planning Guidelines for Debugging Tools
Pin Connection Considerations for Board Design x
Device Power-Up Power Pin Connections and Power Supplies Configuration Pin Connections Board-Related Intel® Quartus® Prime Settings Signal Integrity Considerations Board-Level Simulation and Advanced I/O Timing Analysis
Power Pin Connections and Power Supplies x
Decoupling Capacitors PLL Board Design Guidelines Transceiver Board Design Guidelines
Configuration Pin Connections x
Configuration Pin Voltage Level Clock Trace Signal Integrity JTAG Pins MSEL Configuration Mode Pins Other Configuration Pins
JTAG Pins x
JTAG Pin Connections Download Cable Operating Voltage JTAG Signal Buffering
Board-Related Intel® Quartus® Prime Settings x
Unused Pins
Signal Integrity Considerations x
High-Speed Board Design Voltage Reference Pins Simultaneous Switching Noise I/O Termination
I/O and Clock Planning x
Making FPGA Pin Assignments Early Pin Planning and I/O Assignment Analysis I/O Features and Pin Connections Clock and PLL Selection PLL Feature Guidelines Clock Control Features I/O Simultaneous Switching Noise
I/O Features and Pin Connections x
I/O Signaling Type Selectable Standards and Flexible I/O Banks Memory Interfaces Dual-Purpose and Special Pin Connections Intel® Stratix® 10 I/O Features
PLL Feature Guidelines x
Clock Feedback Mode Clock Outputs
Design Entry x
Design Recommendations Using IP Cores Reconfiguration Recommended HDL Coding Styles
Design Implementation, Analysis, Optimization, and Verification x
Selecting a Synthesis Tool Device Resource Utilization Reports Intel® Quartus® Prime Messages Timing Constraints and Analysis Area and Timing Optimization Preserving Performance and Reducing Compilation Time Designing with Intel® Hyperflex™ Simulation Power Analysis Power Optimization
Timing Constraints and Analysis x
Recommended Timing Optimization and Analysis Assignments
Power Optimization x
Device and Design Power Optimization Techniques Intel® Quartus® Prime Power Optimization Techniques
Device and Design Power Optimization Techniques x
Device Speed Grade Clock Power Management Memory Power Reduction I/O Power Guidelines
Intel® Quartus® Prime Power Optimization Techniques x
Power Optimization Advisor
Intel® Stratix® 10 Device Design Guidelines

Thermal Management and Design

Table 12.  Temperature Design Checklist
Number Done? Checklist Item
1   Obtain thermal design power and thermal parameters from PTC.
2   Perform thermal simulation to determine a proper cooling solution.

Intel® Stratix® 10 is a multi-chip module, depending on package configuration and design information, power distribution on all dies can be quite different. This feature makes the Intel® Stratix® 10 thermal characteristics design dependent. PTC takes into consideration of your design input, and generates unique thermal parameters for your design in the Thermal Page. You can get power consumption for each die, thermal resistance for all dies (ψJC), cooling solution requirement (ψCA), and maximum allowed package case temperature (Tcase).

The thermal analysis of the Intel® Stratix® 10 device requires you use a Compact Thermal Model (contact your local Intel® representatives to obtain the model) and perform simulation in a Computational Fluid Dynamics (CFD) tool. The result of the CFD analysis gives the Tcase which should be lower than the required value in the PTC Thermal Page. With the simulated Tcase, ψJC, and total package power, you can obtain the actual junction temperature Tj, which needs to stay below your requirement, for example, 95˚C. You can adjust your cooling solution (heat sink design, airflow, and so on) to optimize your thermal design.

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