1.2. Simulation Design Example Components
The simulation design example top-level test file is basic_avl_tb_top.sv. This file instantiates and connects an ATX PLL. It includes a task to send and receive 10 packets. The simulation design example for 40GBASE-KR4 variations also exercises auto-negotiation and link training, if enabled.
File Names |
Description |
---|---|
Testbench and Simulation Files | |
basic_avl_tb_top.sv | Top-level testbench file. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets. The testbench also implements auto-negotiation and link training if enabled in a 40GBASE-KR4/CR4 DUT. |
Testbench Scripts | |
run_vsim.do | The Mentor Graphics* ModelSim* SE or Questa* Intel® FPGA Edition script to run the testbench. |
run_vcs.sh | The Synopsys* VCS* script to run the testbench. |
run_vcsmx.sh | The Synopsys* VCS* MX script (combined Verilog HDL and System Verilog with VHDL) to run the testbench. |
run_ncsim.sh | The Cadence NCSim script to run the testbench. |
run_xcelium.sh | The Cadence Xcelium* script to run the testbench. |