1.5. Simulating the Stratix® 10 LL 40GbE Design Example Testbench
Figure 7. Procedure
Follow these steps to simulate the testbench:
- Change to the testbench simulation directory <design_example_dir>/example_testbench.
- Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Refer to the table "Steps to Simulate the Testbench".
- Analyze the results. The successful testbench sends ten packets, receives ten packets, and displays "Testbench complete."
Note: The successful 40GBASE-KR4/CR4 testbench performs auto-negotiation (if enabled) and link training (if enabled) before performing these packet send and receive actions.
Table 3. Steps to Simulate the Testbench Simulator Instructions ModelSim* SE or QuestaSim* or Questa* Intel® FPGA Edition In the command line, type vsim -do run_vsim.do
If you prefer to simulate without bringing up the ModelSim* GUI, typevsim -c -do run_vsim.do
Cadence NCSim In the command line, type sh run_ncsim.sh Cadence Xcelium* In the command line, type sh run_xcelium.sh Synopsys VCS* / VCS* MX In the command line, type sh run_vcs.sh or sh run_vcsmx.sh Note: run_vcs.sh is only available if you select Verilog as the Generated HDL Format. If you select VHDL as the Generated HDL Format, you must simulate the testbench with a mixed language simulator using run_vcsmx.sh.
The successful test run displays output confirming the following behavior:
- Waiting for RX clock to settle
- Printing PHY status
- Sending 10 packets
- Receiving 10 packets
- Displaying "Testbench complete."
The following sample output illustrates a successful simulation test run. For a 40GBASE-KR4/CR4 IP core variation, additional auto-negotiation and link training messages display if these features are enabled.
#Waiting for RX alignment #RX deskew locked #RX lane alignment locked #TX enabled #**Sending Packet 1... #**Sending Packet 2... #**Sending Packet 3... #**Sending Packet 4... #**Sending Packet 5... #**Sending Packet 6... #**Sending Packet 7... #**Received Packet 1... #**Sending Packet 8... #**Received Packet 2... #**Sending Packet 9... #**Received Packet 3... #**Sending Packet 10... #**Received Packet 4... #**Received Packet 5... #**Received Packet 6... #**Received Packet 7... #**Received Packet 8... #**Received Packet 9... #**Received Packet 10... #** #** Testbench complete. #** #*****************************************