1.3. Hardware Design Example Components
Figure 4. Stratix® 10 LL 40GbE Hardware Design Example High Level Block Diagram
The Stratix® 10 LL 40GbE hardware design example includes the following components:
- Stratix® 10 LL 40GbE IP core.
- Client logic that coordinates the programming of the IP core, and packet generation and checking.
- ATX PLL to drive the device transceiver channel clocks.
- IOPLL to generate a 100 MHz clock from a 50 MHz input clock to the hardware design example.
- JTAG controller that communicates with the Intel® System Console. You communicate with the client logic through the System Console.
File Names |
Description |
---|---|
eth_ex_40 g.qpf | Quartus® Prime project file. |
eth_ex_40 g.qsf | Quartus® Prime project settings file. |
eth_ex_40 g.sdc | Synopsys* Design Constraints file. You can copy and modify this file for your own Stratix® 10 LL 40GbE design. |
eth_ex_40 g.v | Top-level Verilog HDL design example file. |
common/ | Hardware design example support files. |
hwtest/main.tcl | Main file for accessing System Console. |