Visible to Intel only — GUID: uwx1474243451461
Ixiasoft
1.1. Intel® Stratix® 10 TX Devices
1.2. Innovations in Intel® Stratix® 10 TX Devices
1.3. Intel® Stratix® 10 TX Features Summary
1.4. Intel® Stratix® 10 TX Block Diagram
1.5. Intel® Stratix® 10 TX Family Plan
1.6. Intel® Hyperflex™ Core Architecture
1.7. Heterogeneous 3D SiP Transceiver Tiles
1.8. Intel® Stratix® 10 TX Transceivers
1.9. PCI Express Gen1/Gen2/Gen3 Hard IP
1.10. Ethernet MAC, Reed-Solomon FEC for NRZ signals (528, 514) and PAM4 signals (544, 514)
1.11. 10G Ethernet Hard IP
1.12. Interlaken PCS Hard IP
1.13. External Memory and General Purpose I/O
1.14. Adaptive Logic Module (ALM)
1.15. Core Clocking
1.16. Fractional Synthesis PLLs and I/O PLLs
1.17. Internal Embedded Memory
1.18. Variable Precision DSP Block
1.19. Hard Processor System (HPS)
1.20. Power Management
1.21. Device Configuration and Secure Device Manager (SDM)
1.22. Device Security
1.23. Configuration via Protocol Using PCI Express*
1.24. Partial and Dynamic Reconfiguration
1.25. Fast Forward Compile
1.26. Single Event Upset (SEU) Error Detection and Correction
1.27. Document Revision History for the Intel® Stratix® 10 TX Device Overview
Visible to Intel only — GUID: uwx1474243451461
Ixiasoft
1.8. Intel® Stratix® 10 TX Transceivers
Intel® Stratix® 10 TX devices offer up to 144 total full-duplex transceiver channels. These channels provide continuous data rates from 1 Gbps to 28.9 Gbps in NRZ mode and 2 Gbps to 57.8 Gbps in PAM4 mode for chip-to-chip, chip-to-module, and backplane applications. For longer-reach backplane driving applications, advanced adaptive equalization circuits can equalize over 30 dB of system loss.
All transceiver channels feature a dedicated PMA and a hardened PCS.
- The PMA provides primary interfacing capabilities to physical channels.
- The PCS typically handles encoding/decoding, word alignment, and other pre-processing functions before transferring data to the FPGA core fabric.
Within each transceiver tile, the transceivers arrange in four banks of six PMA-PCS groups. A wide variety of bonded and non-bonded data rate configurations are possible within each bank, and within each tile, using a highly configurable clock distribution network.