Stratix® 10 TX Device Overview

Download PDF
ID 683717
Date 9/07/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 TX Device Overview
1. Intel® Stratix® 10 TX Device Overview x
1.1. Intel® Stratix® 10 TX Devices 1.2. Innovations in Intel® Stratix® 10 TX Devices 1.3. Intel® Stratix® 10 TX Features Summary 1.4. Intel® Stratix® 10 TX Block Diagram 1.5. Intel® Stratix® 10 TX Family Plan 1.6. Intel® Hyperflex™ Core Architecture 1.7. Heterogeneous 3D SiP Transceiver Tiles 1.8. Intel® Stratix® 10 TX Transceivers 1.9. PCI Express Gen1/Gen2/Gen3 Hard IP 1.10. Ethernet MAC, Reed-Solomon FEC for NRZ signals (528, 514) and PAM4 signals (544, 514) 1.11. 10G Ethernet Hard IP 1.12. Interlaken PCS Hard IP 1.13. External Memory and General Purpose I/O 1.14. Adaptive Logic Module (ALM) 1.15. Core Clocking 1.16. Fractional Synthesis PLLs and I/O PLLs 1.17. Internal Embedded Memory 1.18. Variable Precision DSP Block 1.19. Hard Processor System (HPS) 1.20. Power Management 1.21. Device Configuration and Secure Device Manager (SDM) 1.22. Device Security 1.23. Configuration via Protocol Using PCI Express* 1.24. Partial and Dynamic Reconfiguration 1.25. Fast Forward Compile 1.26. Single Event Upset (SEU) Error Detection and Correction 1.27. Document Revision History for the Intel® Stratix® 10 TX Device Overview
1.1. Intel® Stratix® 10 TX Devices x
1.1.1. Available Options
1.8. Intel® Stratix® 10 TX Transceivers x
1.8.1. PMA Features 1.8.2. PCS Features
1.19. Hard Processor System (HPS) x
1.19.1. Key Features of the Intel® Stratix® 10 HPS
1. Intel® Stratix® 10 TX Device Overview

1.8.2. PCS Features

Intel® Stratix® 10 TX PMA channels interface with core logic through configurable and bypassable PCS interface layers.

The PCS contains multiple gearbox implementations to decouple the PMA and PCS interface widths. This feature provides the flexibility to implement a wide range of applications with 8, 10, 16, 20, 32, 40, or 64 bit interface width between each transceiver and the core logic.

The PCS also contains hard IP to support a variety of standard and proprietary protocols across a wide range of data rates and encoding schemes. The Standard PCS mode provides support for 8B/10B encoded applications up to 12.5 Gbps. The Enhanced PCS mode supports 64B/66B and 64B/67B encoded applications up to 17.4 Gbps. The enhanced PCS mode also includes an integrated 10GBASE-KR/40GBASE-KR4 Forward Error Correction (FEC) circuit. For highly customized implementations, a PCS Direct mode provides an interface up to 64 bits wide to allow for custom encoding and support for data rates up to 28.9 Gbps.

For more information about the PCS-Core interface or the double rate transfer mode, refer to the Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide, and the Intel® Stratix® 10 E-Tile Transceiver PHY User Guide.

Table 8.  Transceiver PCS Features

PCS Protocol Support

Data Rate (Gbps)

Transmitter Data Path

Receiver Data Path

Standard PCS

0.125 to 12.5

Phase compensation FIFO, byte serializer, 8B/10B encoder, bit-slipper, channel bonding

Rate match FIFO, word-aligner, 8B/10B decoder, byte deserializer, byte ordering

PCI Express Gen1/Gen2 x1, x2, x4, x8, x16

2.5 and 5.0

Same as Standard PCS plus PIPE 2.0 interface to core

Same as Standard PCS plus PIPE 2.0 interface to core

PCI Express Gen3 x1, x2, x4, x8, x16

8.0

Phase compensation FIFO, byte serializer, encoder, scrambler, bit-slipper, gear box, channel bonding, and PIPE 3.0 interface to core, auto speed negotiation

Rate match FIFO (0-600 ppm mode), word-aligner, decoder, descrambler, phase compensation FIFO, block sync, byte deserializer, byte ordering, PIPE 3.0 interface to core, auto speed negotiation

CPRI

0.6144 to 9.8

Same as Standard PCS plus deterministic latency serialization

Same as Standard PCS plus deterministic latency deserialization

Enhanced PCS

2.5 to 17.4

FIFO, channel bonding, bit-slipper, and gear box

FIFO, block sync, bit-slipper, and gear box

10GBASE-R

10.3125

FIFO, 64B/66B encoder, scrambler, FEC, and gear box

FIFO, 64B/66B decoder, descrambler, block sync, FEC, and gear box

Interlaken

4.9 to 17.4

FIFO, channel bonding, frame generator, CRC-32 generator, scrambler, disparity generator, bit-slipper, and gear box

FIFO, CRC-32 checker, frame sync, descrambler, disparity checker, block sync, and gear box

SFI-S/SFI-5.2

11.3

FIFO, channel bonding, bit-slipper, and gear box

FIFO, bit-slipper, and gear box

IEEE 1588

1.25 to 10.3125

FIFO (fixed latency), 64B/66B encoder, scrambler, and gear box

FIFO (fixed latency), 64B/66B decoder, descrambler, block sync, and gear box

SDI

up to 12.5

FIFO and gear box

FIFO, bit-slipper, and gear box

GigE

1.25

Same as Standard PCS plus GigE state machine

Same as Standard PCS plus GigE state machine

PCS Direct up to 28.9 Custom Custom
Related Information
Level Two Title