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1.1. Intel® Stratix® 10 TX Devices
1.2. Innovations in Intel® Stratix® 10 TX Devices
1.3. Intel® Stratix® 10 TX Features Summary
1.4. Intel® Stratix® 10 TX Block Diagram
1.5. Intel® Stratix® 10 TX Family Plan
1.6. Intel® Hyperflex™ Core Architecture
1.7. Heterogeneous 3D SiP Transceiver Tiles
1.8. Intel® Stratix® 10 TX Transceivers
1.9. PCI Express Gen1/Gen2/Gen3 Hard IP
1.10. Ethernet MAC, Reed-Solomon FEC for NRZ signals (528, 514) and PAM4 signals (544, 514)
1.11. 10G Ethernet Hard IP
1.12. Interlaken PCS Hard IP
1.13. External Memory and General Purpose I/O
1.14. Adaptive Logic Module (ALM)
1.15. Core Clocking
1.16. Fractional Synthesis PLLs and I/O PLLs
1.17. Internal Embedded Memory
1.18. Variable Precision DSP Block
1.19. Hard Processor System (HPS)
1.20. Power Management
1.21. Device Configuration and Secure Device Manager (SDM)
1.22. Device Security
1.23. Configuration via Protocol Using PCI Express*
1.24. Partial and Dynamic Reconfiguration
1.25. Fast Forward Compile
1.26. Single Event Upset (SEU) Error Detection and Correction
1.27. Document Revision History for the Intel® Stratix® 10 TX Device Overview
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1.19. Hard Processor System (HPS)
The Hard Processor System (HPS) in select Intel® Stratix® 10 TX devices is Intel’s third generation HPS. Leveraging the performance of Intel 14 nm tri-gate technology, the HPS provides more than double the performance of previous generation devices with an integrated quad-core 64-bit Arm* Cortex* -A53. The HPS also enables system-wide hardware virtualization capabilities by adding a system memory management unit. These architecture improvements ensure that Intel® Stratix® 10 TX devices meet the requirements of current and future embedded markets, including wireless and wireline communications, datacenter acceleration, and numerous military applications.
Figure 18. HPS Block Diagram