Stratix® 10 TX Device Overview

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ID 683717
Date 9/07/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 TX Device Overview
1. Intel® Stratix® 10 TX Device Overview x
1.1. Intel® Stratix® 10 TX Devices 1.2. Innovations in Intel® Stratix® 10 TX Devices 1.3. Intel® Stratix® 10 TX Features Summary 1.4. Intel® Stratix® 10 TX Block Diagram 1.5. Intel® Stratix® 10 TX Family Plan 1.6. Intel® Hyperflex™ Core Architecture 1.7. Heterogeneous 3D SiP Transceiver Tiles 1.8. Intel® Stratix® 10 TX Transceivers 1.9. PCI Express Gen1/Gen2/Gen3 Hard IP 1.10. Ethernet MAC, Reed-Solomon FEC for NRZ signals (528, 514) and PAM4 signals (544, 514) 1.11. 10G Ethernet Hard IP 1.12. Interlaken PCS Hard IP 1.13. External Memory and General Purpose I/O 1.14. Adaptive Logic Module (ALM) 1.15. Core Clocking 1.16. Fractional Synthesis PLLs and I/O PLLs 1.17. Internal Embedded Memory 1.18. Variable Precision DSP Block 1.19. Hard Processor System (HPS) 1.20. Power Management 1.21. Device Configuration and Secure Device Manager (SDM) 1.22. Device Security 1.23. Configuration via Protocol Using PCI Express* 1.24. Partial and Dynamic Reconfiguration 1.25. Fast Forward Compile 1.26. Single Event Upset (SEU) Error Detection and Correction 1.27. Document Revision History for the Intel® Stratix® 10 TX Device Overview
1.1. Intel® Stratix® 10 TX Devices x
1.1.1. Available Options
1.8. Intel® Stratix® 10 TX Transceivers x
1.8.1. PMA Features 1.8.2. PCS Features
1.19. Hard Processor System (HPS) x
1.19.1. Key Features of the Intel® Stratix® 10 HPS
1. Intel® Stratix® 10 TX Device Overview

1.13. External Memory and General Purpose I/O

Intel® Stratix® 10 TX devices offer substantial external memory bandwidth, supporting DDR4 memory interfaces running at up to 2666 Mbps. For external memory interface and LVDS restrictions, see AN 906: Intel Stratix 10 GX 400, SX 400, and TX 400 Routing and Designing Floorplan Guidelines .

This bandwidth is provided along with the ease of design, lower power, and resource efficiencies of hardened high-performance memory controllers. The external memory interfaces can be configured up to a maximum width of 144 bits when using either hard or soft memory controllers.

Figure 13. Hard Memory Controller

Each I/O bank contains 48 general purpose I/Os and a high-efficiency hard memory controller capable of supporting many different memory types, each with different performance capabilities. The hard memory controller is also capable of being bypassed and replaced by a soft controller implemented in user logic. The I/Os each have a hardened double data rate (DDR) read/write path (PHY) capable of performing key memory interface functionality such as:

  • Read/write leveling
  • FIFO buffering to lower latency and improve margin
  • Timing calibration
  • On-chip termination

The timing calibration is aided by the inclusion of hard microcontrollers based on Intel’s Nios® II technology, specifically tailored to control the calibration of multiple memory interfaces. This calibration allows the Intel® Stratix® 10 TX device to compensate for any changes in process, voltage, or temperature either within the device itself, or within the external memory device. The advanced calibration algorithms ensure maximum bandwidth and robust timing margin across all operating conditions.

Table 9.  External Memory Interface PerformanceThe listed speeds are for the 1-rank case.

Interface

Controller Type

Performance

(maximum rate possible)

DDR4

Hard

2666 Mbps

DDR3

Hard

2133 Mbps

QDRII+

Soft

1,100 Mtps

QDRII+ Xtreme

Soft

1,266 Mtps

QDRIV

Soft

2,133 Mtps

RLDRAM III

Soft

2400 Mbps

RLDRAM II

Soft

533 Mbps

In addition to parallel memory interfaces, Intel® Stratix® 10 TX devices support serial memory technologies such as the Hybrid Memory Cube (HMC). The HMC is supported by the high-speed serial transceivers, which connect up to four HMC links, with each link running at data rates of 15 Gbps (HMC short reach specification).

Intel® Stratix® 10 TX devices also feature general purpose I/Os capable of supporting a wide range of single-ended and differential I/O interfaces. LVDS rates up to 1.6 Gbps are supported, with each pair of pins having both a differential driver and a differential input buffer. This enables configurable direction for each LVDS pair.

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