Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

8.2.9.3. SDRAM L3 Firewalls

All data that is routed to the SDRAM scheduler must pass through the firewalls.

The SDRAM L3 firewalls define memory access regions in the SDRAM. Each SDRAM L3 interconnect master has its own memory access regions, independent of the other masters. The firewalls define whether each memory access region is protected or unprotected relative to its master. The number of available memory access regions for each master is shown in the following table.

Table 54.  Memory Access Regions for SDRAM Masters
SDRAM L3 Interconnect Master Number of Memory Access Regions
MPU 4
Main L3 interconnect (including the FPGA-to-HPS bridge) 8
FPGA-to-SDRAM port 0 4
FPGA-to-SDRAM port 1 4
FPGA-to-SDRAM port 2 4

The SDRAM L3 interconnect regulates access to the hard memory controller with the firewalls, which support secure regions in the SDRAM address space. Accesses to the SDRAM pass through the firewalls and then through the scheduler.