Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

A.4.4.3.2. Quad SPI Flash Delay Configuration

The delay register in the quad SPI controller configures relative delay of the generation of the master output signals. All timings are defined in cycles of l4_main_clk.

The quad SPI flash memory must meet the following timing requirements:

  • TSLCH: 20 ns
    • TSLCH is used to calculate the init field (delay[7:0]) in the delay register. The init field represents the delay in l4_main_clk clocks between pulling the device chip select (qspi_n_ss_out) low and the first bit transfer.
  • TCHSH: 20 ns
    • TCHSH is used to calculate the after field (delay[15:8]) in the delay register. The after field represents the delay in the l4_main_clk clocks between last bit of the current transaction and the deassertion of the device chip select (qspi_n_ss_out).
  • TSHSL: 200 ns
    • TSHSL is used to calculate the nss (delay[31:24]) field in the delay register and is the delay in the l4_main_clk clocks for the length that the master mode chip select outputs are deasserted between transactions.
  • Tqspi_ref_clk is the master reference clock/external clock, l4_main_clk.

The formulas to calculate the fields in the delay register are:

delay[7:0]= init = TSLCH/Tqspi_ref_clk

delay[15:8]= after = TCHSH/Tqspi_ref_clk

delay[31:24]= nss = (TSHSL - Tqspi_clk)/Tqspi_ref_clk

Table 320.  Quad SPI Flash Delay Configuration for Device Delay (delay) Register

CSEL [3:0] Fuse Values

HPS CLK Fuse Value

Input Clock Range

Tqspi_ref_clk

(ns)

Tqspi_clk

(ns)

delay[7:0] (init)

delay[15:8] (after)

delay[31:24] (nss)

0x0-0x1 and 0x3-0xF

1 60-200 MHz (Secure Bypass) 5 20 4 4 36
0x2 1 30-100 MHz (Secure PLL) 2.5 10 8 8 76
0x1 0 10-50 MHz (Untouched PLL) 20 80 1 1 6
0x0 and 0x2-0x6, 0xF 0 10-50 MHz (PLL Bypass) 20 80 1 1 6

0x7

0 10-15 MHz 2.5 10 8 8 76

0x8

0 15-20 MHz 2.5 10 8 8 76
0x9 0 20-25 MHz 2.5 10 8 8 76
0xA 0 25-30 MHz 2.5 10 8 8 76
0xB 0 30-35 MHz 2.5 10 8 8 76
0xC 0 35-40 MHz 2.5 10 8 8 76
0xD 0 40-45 MHz 2.5 10 8 8 76
0xE 0 45-50 MHz 2.5 10 8 8 76

Read data capture delay is also configured when booting from QSPI. Depending on the CSEL and HPS_CLK fuse values, the Boot ROM configures the delay field of the rddatacap register in the QSPI differently. When you configure the CSEL and HPS_CLK fuses to enable the PLL, the boot ROM calibrates the interface by reading the QSPI signal for all delay values of the rddatacap register. The Boot ROM analyzes all of the delay values that return a valid signature and uses the delay value in the middle of the valid window as the value it programs into the delay field of the rddatacap register. If the PLL is not enabled, then the Boot ROM leaves the rddatacap register untouched.