Intel® Arria® 10 Hard Processor System Technical Reference Manual

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ID 683711
Date 8/28/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 Hard Processor System Technical Reference Manual Revision History 2. Introduction to the Hard Processor System 3. Clock Manager 4. Reset Manager 5. FPGA Manager 6. System Manager 7. SoC Security 8. System Interconnect 9. HPS-FPGA Bridges 10. Cortex*-A9 Microprocessor Unit Subsystem 11. CoreSight* Debug and Trace 12. Error Checking and Correction Controller 13. On-Chip Memory 14. NAND Flash Controller 15. SD/MMC Controller 16. Quad SPI Flash Controller 17. DMA Controller 18. Ethernet Media Access Controller 19. USB 2.0 OTG Controller 20. SPI Controller 21. I2C Controller 22. UART Controller 23. General-Purpose I/O Interface 24. Timer 25. Watchdog Timer 26. Hard Processor System I/O Pin Multiplexing 27. Introduction to the HPS Component 28. Instantiating the HPS Component 29. HPS Component Interfaces 30. Simulating the HPS Component A. Booting and Configuration
2. Introduction to the Hard Processor System x
2.1. Features of the HPS 2.2. HPS Block Diagram and System Integration 2.3. Endian Support 2.4. Introduction to the Hard Processor System Address Map
2.2. HPS Block Diagram and System Integration x
2.2.1. HPS Block Diagram 2.2.2. Cortex-A9 MPCore 2.2.3. HPS Interfaces 2.2.4. System Interconnect 2.2.5. On-Chip Memory 2.2.6. Flash Memory Controllers 2.2.7. Support Peripherals 2.2.8. Interface Peripherals 2.2.9. CoreSight Debug and Trace 2.2.10. Hard Processor System I/O Pin Multiplexing
2.2.3. HPS Interfaces x
2.2.3.1. HPS–FPGA Memory-Mapped Interfaces 2.2.3.2. Other HPS Interfaces
2.2.4. System Interconnect x
2.2.4.1. Arria 10 HPS SDRAM L3 Interconnect
2.2.4.1. Arria 10 HPS SDRAM L3 Interconnect x
2.2.4.1.1. SDRAM Adapter 2.2.4.1.2. SDRAM Scheduler
2.2.5. On-Chip Memory x
2.2.5.1. On-Chip RAM 2.2.5.2. Boot ROM
2.2.6. Flash Memory Controllers x
2.2.6.1. NAND Flash Controller 2.2.6.2. Quad SPI Flash Controller 2.2.6.3. SD/MMC Controller
2.2.7. Support Peripherals x
2.2.7.1. Clock Manager 2.2.7.2. Reset Manager 2.2.7.3. Security Manager 2.2.7.4. System Manager 2.2.7.5. System Timers 2.2.7.6. System Watchdog Timers 2.2.7.7. DMA Controller 2.2.7.8. FPGA Manager 2.2.7.9. Error Checking and Correction Controller
2.2.8. Interface Peripherals x
2.2.8.1. EMACs 2.2.8.2. USB Controllers 2.2.8.3. I2C Controllers 2.2.8.4. UARTs 2.2.8.5. SPI Master Controllers 2.2.8.6. SPI Slave Controllers 2.2.8.7. GPIO Interfaces
2.4. Introduction to the Hard Processor System Address Map x
2.4.1. HPS Address Spaces 2.4.2. HPS Peripheral Region Address Map
2.4.1. HPS Address Spaces x
2.4.1.1. SDRAM Address Space 2.4.1.2. MPU Address Space 2.4.1.3. FPGA Slaves Address Space 2.4.1.4. LWFPGA Slaves Address Space 2.4.1.5. L3 Address Space
3. Clock Manager x
3.1. Features of the Clock Manager 3.2. Clock Manager Block Diagram and System Integration 3.3. Functional Description of the Clock Manager 3.4. Clock Manager Address Map and Register Definitions
3.2. Clock Manager Block Diagram and System Integration x
3.2.1. L4 Peripheral Clocks 3.2.2. Boot Clock
3.2.2. Boot Clock x
3.2.2.1. Updating PLL Settings without a System Reset 3.2.2.2. MPU Clock Scaling
3.3. Functional Description of the Clock Manager x
3.3.1. Clock Manager Building Blocks 3.3.2. PLL Integration 3.3.3. Hardware-Managed and Software-Managed Clocks 3.3.4. Hardware Sequenced Clock Groups 3.3.5. Software Sequenced Clocks 3.3.6. Resets 3.3.7. Security 3.3.8. Interrupts
3.3.1. Clock Manager Building Blocks x
3.3.1.1. PLLs 3.3.1.2. FREF, FVCO, and FOUT Equations 3.3.1.3. Clock Gating
4. Reset Manager x
4.1. Reset Manager Block Diagram and System Integration 4.2. Functional Description of the Reset Manager 4.3. Reset Manager Address Map and Register Definitions
4.1. Reset Manager Block Diagram and System Integration x
4.1.1. Reset Controller 4.1.2. Security Reset Functions 4.1.3. Module Reset Signals 4.1.4. Slave Interface and Status Register
4.1.3. Module Reset Signals x
4.1.3.1. Modules Requiring Software Deassert
4.2. Functional Description of the Reset Manager x
4.2.1. Reset Sequencing 4.2.2. Reset Pins 4.2.3. Reset Effects 4.2.4. Reset Handshaking
4.2.1. Reset Sequencing x
4.2.1.1. Cold Reset Assertion Sequence 4.2.1.2. Warm Reset Assertion Sequence 4.2.1.3. Cold and Warm Reset Deassertion Sequence
5. FPGA Manager x
5.1. Features of the FPGA Manager 5.2. FPGA Manager Block Diagram and System Integration 5.3. Functional Description of the FPGA Manager 5.4. FPGA Manager Address Map and Register Definitions
5.3. Functional Description of the FPGA Manager x
5.3.1. FPGA Configuration 5.3.2. FPGA Status 5.3.3. Error Message Extraction 5.3.4. Data AES Decryption 5.3.5. Boot Handshake 5.3.6. General Purpose I/O 5.3.7. Clock 5.3.8. Reset
6. System Manager x
6.1. Features of the System Manager 6.2. System Manager Block Diagram and System Integration 6.3. Functional Description of the System Manager 6.4. System Manager Address Map and Register Definitions
6.3. Functional Description of the System Manager x
6.3.1. Boot Configuration and System Information 6.3.2. Additional Module Control 6.3.3. Boot ROM Code 6.3.4. FPGA Interface Enables 6.3.5. ECC and Parity Control 6.3.6. Preloader Handoff Information 6.3.7. Clocks 6.3.8. Resets
6.3.2. Additional Module Control x
6.3.2.1. DMA Controller 6.3.2.2. NAND Flash Controller 6.3.2.3. EMAC 6.3.2.4. USB 2.0 OTG Controller 6.3.2.5. SD/MMC Controller 6.3.2.6. Watchdog Timer
6.3.3. Boot ROM Code x
6.3.3.1. Controlling the Boot Memory Map Through the System Interconnect
7. SoC Security x
7.1. Security Manager 7.2. Security System Extensions
7.1. Security Manager x
7.1.1. Security Manager Block Diagram 7.1.2. Functional Overview 7.1.3. Functional Description
7.1.3. Functional Description x
7.1.3.1. Secure Initialization Overview 7.1.3.2. Security State 7.1.3.3. Secure Debug 7.1.3.4. Reset Manager 7.1.3.5. Clock Configuration 7.1.3.6. FPGA Security Features 7.1.3.7. Secure Boot 7.1.3.8. Anti-Tamper
7.1.3.1. Secure Initialization Overview x
7.1.3.1.1. Secure Fuses
7.1.3.2. Security State x
7.1.3.2.1. Security Check 7.1.3.2.2. Secure Serial Interface
7.1.3.3. Secure Debug x
7.1.3.3.1. MPU 7.1.3.3.2. JTAG
7.1.3.7. Secure Boot x
7.1.3.7.1. Boot Configuration 7.1.3.7.2. Secure Boot Process 7.1.3.7.3. Authentication and Decryption
7.2. Security System Extensions x
7.2.1. TrustZone* 7.2.2. Arria 10 HPS Secure Firewalls
7.2.1. TrustZone* x
7.2.1.1. Secure Partitioning 7.2.1.2. Virtual Processor Operation
7.2.1.1. Secure Partitioning x
7.2.1.1.1. Secure Bus Accesses 7.2.1.1.2. Secure Cache Accesses
7.2.2. Arria 10 HPS Secure Firewalls x
7.2.2.1. Firewall Diagrams 7.2.2.2. Secure Transaction Protection 7.2.2.3. Privilege Filter 7.2.2.4. Master Security Policy 7.2.2.5. Secure Interconnect Reset
7.2.2.2. Secure Transaction Protection x
7.2.2.2.1. Peripheral and System Firewalls 7.2.2.2.2. HPS-to-FPGA Firewall 7.2.2.2.3. On-Chip RAM Firewall 7.2.2.2.4. SDRAM Firewall
7.2.2.2.1. Peripheral and System Firewalls x
7.2.2.2.1.1. Secure Transaction Example 7.2.2.2.1.2. Non-secure Transaction Configuration
7.2.2.2.3. On-Chip RAM Firewall x
7.2.2.2.3.1. On-Chip RAM Transaction Configuration
8. System Interconnect x
8.1. About the System Interconnect 8.2. Functional Description of the System Interconnect 8.3. Configuring the System Interconnect 8.4. System Interconnect Address Map and Register Definitions
8.1. About the System Interconnect x
8.1.1. Features of the System Interconnect 8.1.2. System Interconnect Block Diagram and System Integration 8.1.3. Arria 10 HPS Secure Firewalls 8.1.4. About the Rate Adapters 8.1.5. About the SDRAM L3 Interconnect 8.1.6. About Arbitration and Quality of Service 8.1.7. About the Service Network 8.1.8. About the Observation Network
8.1.2. System Interconnect Block Diagram and System Integration x
8.1.2.1. System Interconnect Block Diagram 8.1.2.2. Connectivity 8.1.2.3. System Interconnect Architecture
8.1.2.2. Connectivity x
8.1.2.2.1. Arria 10 HPS Master-to-Slave Connectivity Matrix 8.1.2.2.2. On-Chip RAM 8.1.2.2.3. Peripherals Connections 8.1.2.2.4. System Connections 8.1.2.2.5. HPS-to-FPGA Bridge 8.1.2.2.6. SDRAM Connections
8.1.2.3. System Interconnect Architecture x
8.1.2.3.1. SDRAM L3 Interconnect Architecture
8.1.5. About the SDRAM L3 Interconnect x
8.1.5.1. Features of the SDRAM L3 Interconnect 8.1.5.2. SDRAM L3 Interconnect Block Diagram and System Integration 8.1.5.3. About the SDRAM Scheduler
8.2. Functional Description of the System Interconnect x
8.2.1. System Interconnect Address Spaces 8.2.2. Secure Transaction Protection 8.2.3. System Interconnect Master Properties 8.2.4. System Interconnect Slave Properties 8.2.5. System Interconnect Clocks 8.2.6. System Interconnect Resets 8.2.7. Functional Description of the Rate Adapters 8.2.8. Functional Description of the Firewalls 8.2.9. Functional Description of the SDRAM L3 Interconnect 8.2.10. Functional Description of the Arbitration Logic 8.2.11. Functional Description of the QoS Generators 8.2.12. Functional Description of the Observation Network
8.2.1. System Interconnect Address Spaces x
8.2.1.1. Arria 10 HPS Available Address Maps 8.2.1.2. Arria 10 HPS L3 Address Space 8.2.1.3. MPU Address Space 8.2.1.4. SDRAM Address Space 8.2.1.5. Address Remapping
8.2.1.5. Address Remapping x
8.2.1.5.1. Memory Map Remap Bits
8.2.3. System Interconnect Master Properties x
8.2.3.1. Master Caching and Buffering Overrides
8.2.5. System Interconnect Clocks x
8.2.5.1. List of Main L3 Interconnect Clocks 8.2.5.2. List of SDRAM L3 Interconnect Clocks
8.2.8. Functional Description of the Firewalls x
8.2.8.1. Security
8.2.8.1. Security x
8.2.8.1.1. Slave Security 8.2.8.1.2. Master Security
8.2.9. Functional Description of the SDRAM L3 Interconnect x
8.2.9.1. Functional Description of the SDRAM Scheduler 8.2.9.2. Functional Description of the SDRAM Adapter 8.2.9.3. SDRAM L3 Firewalls 8.2.9.4. SDRAM L3 Interconnect Resets
8.2.9.1. Functional Description of the SDRAM Scheduler x
8.2.9.1.1. Monitors for Mutual Exclusion 8.2.9.1.2. Arbitration and Quality of Service in the SDRAM Scheduler
8.2.9.1.1. Monitors for Mutual Exclusion x
8.2.9.1.1.1. Exclusive Access Support
8.2.9.2. Functional Description of the SDRAM Adapter x
8.2.9.2.1. ECC 8.2.9.2.2. SDRAM Adapter Interrupt Support 8.2.9.2.3. SDRAM Adapter Clocks
8.2.9.2.1. ECC x
8.2.9.2.1.1. ECC Write Behavior 8.2.9.2.1.2. ECC Read Behavior
8.2.11. Functional Description of the QoS Generators x
8.2.11.1. QoS Generators in the Interconnect Architecture 8.2.11.2. QoS Mechanisms 8.2.11.3. QoS Generator Modes
8.2.11.2. QoS Mechanisms x
8.2.11.2.1. Packet Urgency 8.2.11.2.2. Pressure Propagation 8.2.11.2.3. Hurry
8.2.11.3. QoS Generator Modes x
8.2.11.3.1. Limiter Mode 8.2.11.3.2. Regulator Mode 8.2.11.3.3. Fixed Mode
8.2.12. Functional Description of the Observation Network x
8.2.12.1. Probes 8.2.12.2. Packet Tracing, Profiling, and Statistics 8.2.12.3. Packet Alarms 8.2.12.4. Error Logging
8.2.12.2. Packet Tracing, Profiling, and Statistics x
8.2.12.2.1. Packet Filtering 8.2.12.2.2. Statistics Collection 8.2.12.2.3. Transaction Profiling
8.2.12.2.3. Transaction Profiling x
8.2.12.2.3.1. Profiling Transaction Latency 8.2.12.2.3.2. Profiling Pending Transactions
8.3. Configuring the System Interconnect x
8.3.1. Configuring the Rate Adapters 8.3.2. Configuring the SDRAM Scheduler 8.3.3. Configuring the Hard Memory Controller 8.3.4. Configuring the Quality of Service Logic
8.3.2. Configuring the SDRAM Scheduler x
8.3.2.1. FPGA Port Configuration 8.3.2.2. Memory Timing Configuration 8.3.2.3. Configuring SDRAM Burst Sizes
8.3.3. Configuring the Hard Memory Controller x
8.3.3.1. SDRAM Adapter Memory Mapped Registers 8.3.3.2. Sharing I/Os between the EMIF and the FPGA
8.3.4. Configuring the Quality of Service Logic x
8.3.4.1. Programming QoS Limiter Mode 8.3.4.2. Programming QoS Regulator Mode 8.3.4.3. Programming QoS Fixed Mode 8.3.4.4. Bandwidth and Saturation 8.3.4.5. QoS Generator Registers 8.3.4.6. QoS Programming Examples
8.3.4.6. QoS Programming Examples x
8.3.4.6.1. Example: One Master Always Takes Precedence 8.3.4.6.2. Example: Tuning for Specific Throughput Requirements
9. HPS-FPGA Bridges x
9.1. Features of the HPS-FPGA Bridges 9.2. Arria 10 HPS-FPGA Bridges Block Diagram and System Integration 9.3. Functional Description of the HPS-FPGA Bridges 9.4. HPS-FPGA Bridges Address Map and Register Definitions for Arria 10
9.3. Functional Description of the HPS-FPGA Bridges x
9.3.1. Functional Description of the FPGA-to-HPS Bridge 9.3.2. Functional Description of the HPS-to-FPGA Bridge 9.3.3. Functional Description of the Lightweight HPS-to-FPGA Bridge 9.3.4. Clocks and Resets 9.3.5. Data Width Sizing
9.3.1. Functional Description of the FPGA-to-HPS Bridge x
9.3.1.1. FPGA-to-HPS Access to ACP 9.3.1.2. FPGA-to-HPS Bridge Slave Signals
9.3.2. Functional Description of the HPS-to-FPGA Bridge x
9.3.2.1. HPS-to-FPGA Bridge Master Signals
9.3.3. Functional Description of the Lightweight HPS-to-FPGA Bridge x
9.3.3.1. Lightweight HPS-to-FPGA Bridge Master Signals
9.3.4. Clocks and Resets x
9.3.4.1. FPGA-to-HPS Bridge Clocks and Resets 9.3.4.2. HPS-to-FPGA Bridge Clocks and Resets 9.3.4.3. Lightweight HPS-to-FPGA Bridge Clocks and Resets 9.3.4.4. Taking HPS-FPGA Bridges Out of Reset
9.3.5. Data Width Sizing x
9.3.5.1. Ready Latency Support
10. Cortex*-A9 Microprocessor Unit Subsystem x
10.1. Features of the Cortex-A9 MPU Subsystem 10.2. Cortex*-A9 MPU Subsystem Block Diagram and System Integration 10.3. Cortex*-A9 MPCore 10.4. L2 Cache 10.5. CPU Prefetch 10.6. TrustZone* 10.7. Debugging Modules 10.8. Clocks 10.9. Cortex*-A9 MPU Subsystem Register Implementation
10.2. Cortex*-A9 MPU Subsystem Block Diagram and System Integration x
10.2.1. Cortex*-A9 MPU Subsystem with System Interconnect 10.2.2. Cortex*-A9 MPU Subsystem Internals
10.3. Cortex*-A9 MPCore x
10.3.1. Functional Description 10.3.2. Implementation Details 10.3.3. Cortex*-A9 Processor 10.3.4. Interactive Debugging Features 10.3.5. L1 Caches 10.3.6. Preload Engine 10.3.7. Floating Point Unit 10.3.8. NEON* Multimedia Processing Engine 10.3.9. Memory Management Unit 10.3.10. Performance Monitoring Unit 10.3.11. Arm* Cortex* -A9 MPCore* Timers 10.3.12. Generic Interrupt Controller 10.3.13. Global Timer 10.3.14. Snoop Control Unit 10.3.15. Accelerator Coherency Port
10.3.3. Cortex*-A9 Processor x
10.3.3.1. Reset
10.3.5. L1 Caches x
10.3.5.1. Cache Latency
10.3.8. NEON* Multimedia Processing Engine x
10.3.8.1. Single Instruction, Multiple Data (SIMD) Processing 10.3.8.2. Features of the NEON* MPE
10.3.9. Memory Management Unit x
10.3.9.1. TLBs Supported By the MMU 10.3.9.2. TLB Features 10.3.9.3. The Boot Region 10.3.9.4. The SDRAM Region 10.3.9.5. The FPGA Slaves Region 10.3.9.6. The HPS Peripherals Region
10.3.9.3. The Boot Region x
10.3.9.3.1. Boot ROM Mapping
10.3.11. Arm* Cortex* -A9 MPCore* Timers x
10.3.11.1. Functional Description 10.3.11.2. Implementation Details
10.3.12. Generic Interrupt Controller x
10.3.12.1. Functional Description 10.3.12.2. Implementation Details
10.3.12.2. Implementation Details x
10.3.12.2.1. GIC Interrupt Map for the Arria 10 SoC HPS
10.3.13. Global Timer x
10.3.13.1. Functional Description 10.3.13.2. Implementation Details
10.3.14. Snoop Control Unit x
10.3.14.1. Functional Description 10.3.14.2. Implementation Details
10.3.14.1. Functional Description x
10.3.14.1.1. Coherent Memory, Snoop Control Unit, and Accelerator Coherency Port
10.3.15. Accelerator Coherency Port x
10.3.15.1. AxUSER and AxCACHE Attributes 10.3.15.2. AxPROT Attributes 10.3.15.3. Cache Coherency for ACP Shared Requests 10.3.15.4. AXI Master Configuration for ACP Access 10.3.15.5. Burst Sizes and Byte Strobes 10.3.15.6. Exclusive and Locked Accesses 10.3.15.7. Avoiding ACP Dependency Lockup
10.3.15.4. AXI Master Configuration for ACP Access x
10.3.15.4.1. Configuring AxCACHE[3:0] Sideband Signals for Coherent Accesses 10.3.15.4.2. Configuring AxUSER[4:0] Sideband Signals 10.3.15.4.3. Configuring AxPROT[2:0] Sideband Signals for Coherent Accesses
10.3.15.5. Burst Sizes and Byte Strobes x
10.3.15.5.1. Recommended Burst Types
10.4. L2 Cache x
10.4.1. Functional Description
10.4.1. Functional Description x
10.4.1.1. Cache Controller Configuration 10.4.1.2. Single Event Upset Protection 10.4.1.3. L2 Cache Parity 10.4.1.4. L2 Cache Lockdown Capabilities 10.4.1.5. L2 Cache Event Monitoring 10.4.1.6. L2 Cache Address Filtering 10.4.1.7. Cache Latency
10.4.1.1. Cache Controller Configuration x
10.4.1.1.1. Implementation Details
10.4.1.1.1. Implementation Details x
10.4.1.1.1.1. L2 Cache Event Monitoring
10.6. TrustZone* x
10.6.1. Secure Partitioning 10.6.2. Virtual Processor Operation 10.6.3. Secure Debug
10.6.1. Secure Partitioning x
10.6.1.1. Secure Bus Accesses 10.6.1.2. Secure Cache Accesses
10.7. Debugging Modules x
10.7.1. Program Trace 10.7.2. Event Trace 10.7.3. Cross-Triggering
10.9. Cortex*-A9 MPU Subsystem Register Implementation x
10.9.1. Cortex*-A9 MPU Subsystem Address Map for Arria 10 10.9.2. L2 Cache Controller Address Map for Arria 10
11. CoreSight* Debug and Trace x
11.1. Features of CoreSight* Debug and Trace 11.2. Arm* CoreSight* Documentation 11.3. CoreSight Debug and Trace Block Diagram and System Integration 11.4. Functional Description of CoreSight Debug and Trace 11.5. CoreSight* Debug and Trace Programming Model 11.6. CoreSight Debug and Trace Address Map and Register Definitions
11.4. Functional Description of CoreSight Debug and Trace x
11.4.1. Debug Access Port 11.4.2. System Trace Macrocell 11.4.3. Trace Funnel 11.4.4. CoreSight Trace Memory Controller 11.4.5. AMBA* Trace Bus Replicator 11.4.6. Trace Port Interface Unit 11.4.7. Embedded Cross Trigger System 11.4.8. Program Trace Macrocell 11.4.9. HPS Debug APB* Interface 11.4.10. FPGA Interface 11.4.11. Debug Clocks 11.4.12. Debug Resets
11.4.1. Debug Access Port x
11.4.1.1. JTAG Connection
11.4.4. CoreSight Trace Memory Controller x
11.4.4.1. Embedded Trace FIFO 11.4.4.2. Embedded Trace Router
11.4.7. Embedded Cross Trigger System x
11.4.7.1. Cross Trigger Interface 11.4.7.2. Cross Trigger Matrix
11.4.10. FPGA Interface x
11.4.10.1. DAP 11.4.10.2. STM 11.4.10.3. FPGA-CTI 11.4.10.4. CTI-NoC 11.4.10.5. TPIU
11.5. CoreSight* Debug and Trace Programming Model x
11.5.1. Coresight Component Address 11.5.2. STM Channels 11.5.3. CTI Trigger Connections to Outside the Debug System 11.5.4. Configuring Embedded Cross-Trigger Connections
11.5.3. CTI Trigger Connections to Outside the Debug System x
11.5.3.1. CTI 11.5.3.2. FPGA-CTI 11.5.3.3. L3-CTI
11.5.4. Configuring Embedded Cross-Trigger Connections x
11.5.4.1. Configuring Trigger Input 0 11.5.4.2. Triggering a Flush of Trace Data to the TPIU 11.5.4.3. Triggering an STM message 11.5.4.4. Triggering a Breakpoint on CPU 1
11.6. CoreSight Debug and Trace Address Map and Register Definitions x
11.6.1. stm Address Map 11.6.2. dap Address Map
12. Error Checking and Correction Controller x
12.1. ECC Controller Features 12.2. ECC Supported Memories 12.3. ECC Controller Block Diagram and System Integration 12.4. ECC Controller Functional Description 12.5. ECC Controller Address Map and Register Descriptions
12.4. ECC Controller Functional Description x
12.4.1. Overview 12.4.2. ECC Structure 12.4.3. Memory Data Initialization 12.4.4. Indirect Memory Access 12.4.5. Error Logging 12.4.6. ECC Controller Interrupts 12.4.7. ECC Controller Initialization and Configuration 12.4.8. ECC Controller Clocks 12.4.9. ECC Controller Reset
12.4.2. ECC Structure x
12.4.2.1. RAM and ECC Memory Organization Example
12.4.4. Indirect Memory Access x
12.4.4.1. Watchdog Timer 12.4.4.2. Data Correction 12.4.4.3. Error Injection 12.4.4.4. Memory Testing 12.4.4.5. Error Checking and Correction Algorithm
12.4.4.4. Memory Testing x
12.4.4.4.1. Peripheral Slave Interface Tests 12.4.4.4.2. Register Interface Tests
12.4.5. Error Logging x
12.4.5.1. Recent Error Address Registers 12.4.5.2. Single-Bit Error Occurrence 12.4.5.3. Single-Bit Error Look-Up Table
12.4.6. ECC Controller Interrupts x
12.4.6.1. Single-Bit Error Interrupts 12.4.6.2. Double-Bit Error Interrupt 12.4.6.3. Interrupt Testing
12.4.6.1. Single-Bit Error Interrupts x
12.4.6.1.1. All Single-Bit Error Interrupt 12.4.6.1.2. LUT Overflow Interrupt 12.4.6.1.3. Counter Match Interrupt
13. On-Chip Memory x
13.1. On-Chip RAM 13.2. Boot ROM 13.3. On-Chip Memory Address Map and Register Definitions
13.1. On-Chip RAM x
13.1.1. Features of the On-Chip RAM 13.1.2. On-Chip RAM Block Diagram and System Integration 13.1.3. Functional Description of the On-Chip RAM
13.1.3. Functional Description of the On-Chip RAM x
13.1.3.1. On-Chip RAM Clocks 13.1.3.2. On-Chip RAM Resets 13.1.3.3. On-Chip RAM Initialization 13.1.3.4. On-Chip RAM Firewall 13.1.3.5. ECC Protection
13.2. Boot ROM x
13.2.1. Features of the Boot ROM 13.2.2. Boot ROM Block Diagram and System Integration 13.2.3. Functional Description of the Boot ROM
13.2.3. Functional Description of the Boot ROM x
13.2.3.1. Boot ROM Clocks 13.2.3.2. Boot ROM Resets
14. NAND Flash Controller x
14.1. NAND Flash Controller Features 14.2. NAND Flash Controller Block Diagram and System Integration 14.3. NAND Flash Controller Signal Descriptions 14.4. Functional Description of the NAND Flash Controller 14.5. NAND Flash Controller Programming Model 14.6. NAND Flash Controller Address Map and Register Definitions
14.4. Functional Description of the NAND Flash Controller x
14.4.1. Discovery and Initialization 14.4.2. Bootstrap Interface 14.4.3. Configuration by Host 14.4.4. Local Memory Buffer 14.4.5. Clocks 14.4.6. Resets 14.4.7. Indexed Addressing 14.4.8. Command Mapping 14.4.9. Data DMA 14.4.10. ECC
14.4.2. Bootstrap Interface x
14.4.2.1. Bootstrap Setting Bits
14.4.3. Configuration by Host x
14.4.3.1. Recommended Bootstrap Settings for 512-Byte Page Device 14.4.3.2. NAND Page Main and Spare Areas
14.4.5. Clocks x
14.4.5.1. Clock Generation 14.4.5.2. Clock Enable 14.4.5.3. Clock Switching
14.4.6. Resets x
14.4.6.1. Taking the NAND Flash Controller Out of Reset
14.4.7. Indexed Addressing x
14.4.7.1. Register Map for Indexed Addressing 14.4.7.2. Indexed Addressing Host Usage
14.4.8. Command Mapping x
14.4.8.1. MAP00 Commands 14.4.8.2. MAP01 Commands 14.4.8.3. MAP10 Commands 14.4.8.4. MAP11 Commands
14.4.8.1. MAP00 Commands x
14.4.8.1.1. MAP00 Command Format 14.4.8.1.2. MAP00 Usage Limitations
14.4.8.2. MAP01 Commands x
14.4.8.2.1. MAP01 Command Format 14.4.8.2.2. MAP01 Usage Limitations
14.4.8.3. MAP10 Commands x
14.4.8.3.1. MAP10 Command Format 14.4.8.3.2. MAP10 Operations 14.4.8.3.3. MAP10 Usage Limitations
14.4.8.4. MAP11 Commands x
14.4.8.4.1. MAP11 Control Format 14.4.8.4.2. MAP11 Usage Limitations
14.4.9. Data DMA x
14.4.9.1. Multi-Transaction DMA Command 14.4.9.2. Burst DMA Command
14.4.9.1. Multi-Transaction DMA Command x
14.4.9.1.1. Command-Data Pair Formats 14.4.9.1.2. Using Multi-Transaction DMA Commands
14.4.10. ECC x
14.4.10.1. Correction Capability, Sector Size, and Check Bit Size 14.4.10.2. ECC Programming Modes 14.4.10.3. Preserving Bad Block Markers 14.4.10.4. Error Correction Status
14.4.10.2. ECC Programming Modes x
14.4.10.2.1. Main Area Transfer Mode 14.4.10.2.2. Spare Area Transfer Mode 14.4.10.2.3. Main+Spare Area Transfer Mode
15. SD/MMC Controller x
15.1. Features of the SD/MMC Controller 15.2. SD/MMC Controller Block Diagram and System Integration 15.3. SD/MMC Controller Signal Description 15.4. Functional Description of the SD/MMC Controller 15.5. SD/MMC Controller Programming Model 15.6. SD/MMC Controller Address Map and Register Definitions
15.1. Features of the SD/MMC Controller x
15.1.1. SD Card Support Matrix 15.1.2. MMC Support Matrix
16. Quad SPI Flash Controller x
16.1. Features of the Quad SPI Flash Controller 16.2. Quad SPI Flash Controller Block Diagram and System Integration 16.3. Quad SPI Flash Controller Signal Description 16.4. Functional Description of the Quad SPI Flash Controller 16.5. Quad SPI Flash Controller Programming Model 16.6. Quad SPI Flash Controller Address Map and Register Definitions
16.4. Functional Description of the Quad SPI Flash Controller x
16.4.1. Overview 16.4.2. Data Slave Interface 16.4.3. SPI Legacy Mode 16.4.4. Register Slave Interface 16.4.5. Local Memory Buffer 16.4.6. DMA Peripheral Request Controller 16.4.7. Arbitration between Direct/Indirect Access Controller and STIG 16.4.8. Configuring the Flash Device 16.4.9. XIP Mode 16.4.10. Write Protection 16.4.11. Data Slave Sequential Access Detection 16.4.12. Clocks 16.4.13. Resets 16.4.14. Interrupts
16.4.2. Data Slave Interface x
16.4.2.1. Direct Access Mode 16.4.2.2. Indirect Access Mode
16.4.2.1. Direct Access Mode x
16.4.2.1.1. Data Slave Remapping Example 16.4.2.1.2. AHB*
16.4.2.2. Indirect Access Mode x
16.4.2.2.1. Indirect Read Operation 16.4.2.2.2. Indirect Write Operation 16.4.2.2.3. Consecutive Reads and Writes
16.4.4. Register Slave Interface x
16.4.4.1. STIG Operation
16.4.8. Configuring the Flash Device x
16.4.8.1. Write Request
16.4.12. Clocks x
16.4.12.1. Clock Gating
16.4.13. Resets x
16.4.13.1. Taking the Quad SPI Flash Controller Out of Reset 16.4.13.2. SRAM Initialization Procedure with ECC Enabled
16.5. Quad SPI Flash Controller Programming Model x
16.5.1. Setting Up the Quad SPI Flash Controller 16.5.2. Indirect Read Operation with DMA Disabled 16.5.3. Indirect Read Operation with DMA Enabled 16.5.4. Indirect Write Operation with DMA Disabled 16.5.5. Indirect Write Operation with DMA Enabled 16.5.6. XIP Mode Operations
16.5.6. XIP Mode Operations x
16.5.6.1. Entering XIP Mode 16.5.6.2. Exiting XIP Mode 16.5.6.3. XIP Mode at Power on Reset
16.5.6.1. Entering XIP Mode x
16.5.6.1.1. Micron Quad SPI Flash Devices with Support for Basic-XIP 16.5.6.1.2. Micron Quad SPI Flash Devices without Support for Basic-XIP 16.5.6.1.3. Winbond Quad SPI Flash Devices 16.5.6.1.4. Spansion Quad SPI Flash Devices
17. DMA Controller x
17.1. Features of the DMA Controller 17.2. DMA Controller Block Diagram and System Integration 17.3. Functional Description of the DMA Controller 17.4. DMA Controller Address Map and Register Definitions
17.3. Functional Description of the DMA Controller x
17.3.1. Peripheral Request Interface
17.3.1. Peripheral Request Interface x
17.3.1.1. Peripheral Request Interface Mapping
17.4. DMA Controller Address Map and Register Definitions x
17.4.1. DMA Controller Address Map and Register Definitions
18. Ethernet Media Access Controller x
18.1. Features of the Ethernet MAC 18.2. EMAC Block Diagram and System Integration 18.3. EMAC Signal Description 18.4. EMAC Internal Interfaces 18.5. Functional Description of the EMAC 18.6. Ethernet MAC Programming Model 18.7. Ethernet MAC Address Map and Register Definitions
18.1. Features of the Ethernet MAC x
18.1.1. MAC 18.1.2. DMA 18.1.3. Management Interface 18.1.4. Acceleration 18.1.5. PHY Interface
18.3. EMAC Signal Description x
18.3.1. HPS EMAC I/O Signals 18.3.2. FPGA EMAC I/O Signals 18.3.3. PHY Management Interface
18.3.3. PHY Management Interface x
18.3.3.1. MDIO Interface 18.3.3.2. I2C External PHY Management Interface
18.4. EMAC Internal Interfaces x
18.4.1. DMA Master Interface 18.4.2. Timestamp Interface 18.4.3. System Manager Configuration Interface
18.6. Ethernet MAC Programming Model x
18.6.1. System Level EMAC Configuration Registers 18.6.2. EMAC FPGA Interface Initialization 18.6.3. EMAC HPS Interface Initialization 18.6.4. DMA Initialization 18.6.5. EMAC Initialization and Configuration 18.6.6. Performing Normal Receive and Transmit Operation 18.6.7. Stopping and Starting Transmission 18.6.8. Programming Guidelines for Energy Efficient Ethernet 18.6.9. Programming Guidelines for Flexible Pulse-Per-Second (PPS) Output
18.6.8. Programming Guidelines for Energy Efficient Ethernet x
18.6.8.1. Entering and Exiting the TX LPI Mode 18.6.8.2. Gating Off the CSR Clock in the LPI Mode
18.6.8.2. Gating Off the CSR Clock in the LPI Mode x
18.6.8.2.1. Gating Off the CSR Clock in the RX LPI Mode 18.6.8.2.2. Gating Off the CSR Clock in the TX LPI Mode
18.6.9. Programming Guidelines for Flexible Pulse-Per-Second (PPS) Output x
18.6.9.1. Generating a Single Pulse on PPS 18.6.9.2. Generating a Pulse Train on PPS 18.6.9.3. Generating an Interrupt without Affecting the PPS
19. USB 2.0 OTG Controller x
19.1. Features of the USB OTG Controller 19.2. USB OTG Controller Block Diagram and System Integration 19.3. USB 2.0 ULPI PHY Signal Description 19.4. Functional Description of the USB OTG Controller 19.5. USB OTG Controller Programming Model 19.6. USB 2.0 OTG Controller Address Map and Register Definitions
19.1. Features of the USB OTG Controller x
19.1.1. Supported PHYS
19.4. Functional Description of the USB OTG Controller x
19.4.1. USB OTG Controller Block Description 19.4.2. Local Memory Buffer 19.4.3. Clocks 19.4.4. Resets 19.4.5. Interrupts
19.4.1. USB OTG Controller Block Description x
19.4.1.1. Master Interface 19.4.1.2. Slave Interface 19.4.1.3. Application Interface Unit 19.4.1.4. Packet FIFO Controller 19.4.1.5. SPRAM 19.4.1.6. MAC 19.4.1.7. Wakeup and Power Control 19.4.1.8. PHY Interface Unit 19.4.1.9. DMA
19.4.1.2. Slave Interface x
19.4.1.2.1. Slave Interface CSR Unit
19.4.1.6. MAC x
19.4.1.6.1. USB Transactions 19.4.1.6.2. Host Protocol 19.4.1.6.3. Device Protocol 19.4.1.6.4. OTG Protocol
19.4.3. Clocks x
19.4.3.1. Clock Gating
19.4.4. Resets x
19.4.4.1. Reset Requirements 19.4.4.2. Hardware Reset 19.4.4.3. Software Reset 19.4.4.4. Taking the USB 2.0 OTG Controller Out of Reset
19.5. USB OTG Controller Programming Model x
19.5.1. Enabling ECC 19.5.2. Enabling SPRAM ECCs 19.5.3. Host Operation 19.5.4. Device Operation
19.5.3. Host Operation x
19.5.3.1. Host Initialization 19.5.3.2. Host Transaction
19.5.4. Device Operation x
19.5.4.1. Device Initialization 19.5.4.2. Device Transaction
19.5.4.2. Device Transaction x
19.5.4.2.1. IN Transactions 19.5.4.2.2. OUT Transactions 19.5.4.2.3. Control Transfers
20. SPI Controller x
20.1. Features of the SPI Controller 20.2. SPI Block Diagram and System Integration 20.3. SPI Controller Signal Description 20.4. Functional Description of the SPI Controller 20.5. SPI Programming Model 20.6. SPI Controller Address Map and Register Definitions
20.2. SPI Block Diagram and System Integration x
20.2.1. SPI Block Diagram
20.3. SPI Controller Signal Description x
20.3.1. Interface to HPS I/O 20.3.2. FPGA Routing
20.4. Functional Description of the SPI Controller x
20.4.1. Protocol Details and Standards Compliance 20.4.2. SPI Controller Overview 20.4.3. Transfer Modes 20.4.4. SPI Master 20.4.5. SPI Slave 20.4.6. Partner Connection Interfaces 20.4.7. DMA Controller Interface 20.4.8. Slave Interface 20.4.9. Clocks and Resets
20.4.2. SPI Controller Overview x
20.4.2.1. Serial Bit-Rate Clocks 20.4.2.2. Transmit and Receive FIFO Buffers 20.4.2.3. SPI Interrupts
20.4.2.1. Serial Bit-Rate Clocks x
20.4.2.1.1. SPI Master Bit-Rate Clock 20.4.2.1.2. SPI Slave Bit-Rate Clock
20.4.3. Transfer Modes x
20.4.3.1. Transmit and Receive 20.4.3.2. Transmit Only 20.4.3.3. Receive Only 20.4.3.4. EEPROM Read
20.4.4. SPI Master x
20.4.4.1. RXD Sample Delay 20.4.4.2. Data Transfers 20.4.4.3. Master SPI and SSP Serial Transfers 20.4.4.4. Master Microwire Serial Transfers
20.4.5. SPI Slave x
20.4.5.1. Slave SPI and SSP Serial Transfers  20.4.5.2. Serial Transfers 20.4.5.3. Glue Logic for Master Port ss_in_n
20.4.6. Partner Connection Interfaces x
20.4.6.1. Motorola SPI Protocol 20.4.6.2. Texas Instruments Synchronous Serial Protocol (SSP) 20.4.6.3. National Semiconductor Microwire Protocol
20.4.8. Slave Interface x
20.4.8.1. Control and Status Register Access 20.4.8.2. Data Register Access
20.4.9. Clocks and Resets x
20.4.9.1. Clock Gating 20.4.9.2. Taking the SPI Controller Out of Reset
20.5. SPI Programming Model x
20.5.1. Master SPI and SSP Serial Transfers 20.5.2. Master Microwire Serial Transfers 20.5.3. Slave SPI and SSP Serial Transfers 20.5.4. Slave Microwire Serial Transfers 20.5.5. Software Control for Slave Selection 20.5.6. DMA Controller Operation
20.5.5. Software Control for Slave Selection x
20.5.5.1. Example: Slave Selection Software Flow for SPI Master 20.5.5.2. Example: Slave Selection Software Flow for SPI Slave
20.5.6. DMA Controller Operation x
20.5.6.1. Transmit FIFO Buffer Underflow 20.5.6.2. Transmit FIFO Watermark 20.5.6.3. Transmit FIFO Buffer Overflow 20.5.6.4. Receive FIFO Buffer Overflow 20.5.6.5. Choosing Receive Watermark Level 20.5.6.6. Receive FIFO Buffer Underflow
20.5.6.2. Transmit FIFO Watermark x
20.5.6.2.1. Example 1: Transmit FIFO Watermark Level = 64 20.5.6.2.2. Example 2: Transmit FIFO Watermark Level = 192
21. I2C Controller x
21.1. Features of the I2C Controller 21.2. I2C Controller Block Diagram and System Integration 21.3. I2C Controller Signal Description 21.4. Functional Description of the I2C Controller 21.5. I2C Controller Programming Model 21.6. I 2 C Controller Address Map and Register Definitions
21.4. Functional Description of the I2C Controller x
21.4.1. Feature Usage 21.4.2. Behavior 21.4.3. Protocol Details 21.4.4. Multiple Master Arbitration 21.4.5. Clock Frequency Configuration 21.4.6. SDA Hold Time 21.4.7. DMA Controller Interface 21.4.8. Clocks 21.4.9. Resets
21.4.2. Behavior x
21.4.2.1. START and STOP Generation 21.4.2.2. Combined Formats
21.4.3. Protocol Details x
21.4.3.1. START and STOP Conditions 21.4.3.2. Addressing Slave Protocol 21.4.3.3. Transmitting and Receiving Protocol 21.4.3.4. START BYTE Transfer Protocol
21.4.3.2. Addressing Slave Protocol x
21.4.3.2.1. 7-Bit Address Format 21.4.3.2.2. 10-Bit Address Format
21.4.3.3. Transmitting and Receiving Protocol x
21.4.3.3.1. Master-Transmitter and Slave-Receiver 21.4.3.3.2. Master-Receiver and Slave-Transmitter
21.4.4. Multiple Master Arbitration x
21.4.4.1. Clock Synchronization
21.4.5. Clock Frequency Configuration x
21.4.5.1. Minimum High and Low Counts
21.4.5.1. Minimum High and Low Counts x
21.4.5.1.1. Calculating High and Low Counts
21.4.9. Resets x
21.4.9.1. Taking the I2C Controller Out of Reset
21.5. I2C Controller Programming Model x
21.5.1. Slave Mode Operation 21.5.2. Master Mode Operation 21.5.3. Disabling the I2C Controller 21.5.4. Abort Transfer 21.5.5. DMA Controller Operation
21.5.1. Slave Mode Operation x
21.5.1.1. Initial Configuration 21.5.1.2. Slave-Transmitter Operation for a Single Byte 21.5.1.3. Slave-Receiver Operation for a Single Byte 21.5.1.4. Slave-Transfer Operation for Bulk Transfers 21.5.1.5. Slave Programming Model
21.5.2. Master Mode Operation x
21.5.2.1. Initial Configuration 21.5.2.2. Dynamic IC_TAR or IC_10BITADDR_MASTER Update 21.5.2.3. Master Transmit and Master Receive 21.5.2.4. Master Programming Model
21.5.5. DMA Controller Operation x
21.5.5.1. Transmit FIFO Underflow 21.5.5.2. Transmit Watermark Level 21.5.5.3. Transmit FIFO Overflow 21.5.5.4. Receive FIFO Overflow 21.5.5.5. Receive Watermark Level 21.5.5.6. Receive FIFO Underflow
22. UART Controller x
22.1. UART Controller Features 22.2. UART Controller Block Diagram and System Integration 22.3. UART Controller Signal Description 22.4. Functional Description of the UART Controller 22.5. DMA Controller Operation 22.6. UART Controller Address Map and Register Definitions
22.3. UART Controller Signal Description x
22.3.1. HPS I/O Pins 22.3.2. FPGA Routing
22.4. Functional Description of the UART Controller x
22.4.1. FIFO Buffer Support 22.4.2. UART(RS232) Serial Protocol 22.4.3. Automatic Flow Control 22.4.4. Clocks 22.4.5. Resets 22.4.6. Interrupts
22.4.3. Automatic Flow Control x
22.4.3.1. RTC Flow Control Trigger 22.4.3.2. Automatic RTS mode 22.4.3.3. Automatic CTS mode
22.4.5. Resets x
22.4.5.1. Taking the UART Controller Out of Reset
22.4.6. Interrupts x
22.4.6.1. Programmable THRE Interrupt
22.5. DMA Controller Operation x
22.5.1. Transmit FIFO Underflow 22.5.2. Transmit Watermark Level 22.5.3. Transmit FIFO Overflow 22.5.4. Receive FIFO Overflow 22.5.5. Receive Watermark Level 22.5.6. Receive FIFO Underflow
22.5.2. Transmit Watermark Level x
22.5.2.1. IIR_FCR.TET = 1 22.5.2.2. IIR_FCR.TET = 3
23. General-Purpose I/O Interface x
23.1. Features of the GPIO Interface 23.2. GPIO Interface Block Diagram and System Integration 23.3. Functional Description of the GPIO Interface 23.4. GPIO Interface Programming Model 23.5. General-Purpose I/O Interface Address Map and Register Definitions
23.3. Functional Description of the GPIO Interface x
23.3.1. Debounce Operation 23.3.2. Pin Directions 23.3.3. Taking the GPIO Interface Out of Reset
24. Timer x
24.1. Features of the Timer 24.2. Timer Block Diagram and System Integration 24.3. Functional Description of the Timer 24.4. Timer Programming Model 24.5. Timer Address Map and Register Definitions
24.3. Functional Description of the Timer x
24.3.1. Clocks 24.3.2. Resets 24.3.3. Interrupts
24.4. Timer Programming Model x
24.4.1. Initialization 24.4.2. Enabling the Timer 24.4.3. Disabling the Timer 24.4.4. Loading the Timer Countdown Value 24.4.5. Servicing Interrupts
24.4.5. Servicing Interrupts x
24.4.5.1. Clearing the Interrupt 24.4.5.2. Checking the Interrupt Status 24.4.5.3. Masking the Interrupt
25. Watchdog Timer x
25.1. Features of the Watchdog Timer 25.2. Watchdog Timer Block Diagram and System Integration 25.3. Functional Description of the Watchdog Timer 25.4. Watchdog Timer Programming Model 25.5. Watchdog Timer Address Map and Register Definitions
25.3. Functional Description of the Watchdog Timer x
25.3.1. Watchdog Timer Counter 25.3.2. Watchdog Timer Pause Mode 25.3.3. Watchdog Timer Clocks 25.3.4. Watchdog Timer Resets
25.3.4. Watchdog Timer Resets x
25.3.4.1. Taking the Watchdog Timer Out of Reset
25.4. Watchdog Timer Programming Model x
25.4.1. Setting the Timeout Period Values 25.4.2. Selecting the Output Response Mode 25.4.3. Enabling and Initially Starting a Watchdog Timer 25.4.4. Reloading a Watchdog Counter 25.4.5. Pausing a Watchdog Timer 25.4.6. Disabling and Stopping a Watchdog Timer 25.4.7. Watchdog Timer State Machine
26. Hard Processor System I/O Pin Multiplexing x
26.1. Features of the HPS I/O Block 26.2. HPS I/O Block Diagram and System Integration 26.3. Functional Description of the HPS I/O 26.4. Test Considerations 26.5. I/O Pin MUX Address Map and Register Definitions for Arria 10
26.3. Functional Description of the HPS I/O x
26.3.1. Dedicated I/O Pins 26.3.2. Shared I/O Pins 26.3.3. FPGA Access 26.3.4. Control Registers 26.3.5. Configuring HPS I/O Multiplexing
26.3.1. Dedicated I/O Pins x
26.3.1.1. Warm Reset Pin 26.3.1.2. Boot Pins
26.3.4. Control Registers x
26.3.4.1. Dedicated Pin MUX Registers 26.3.4.2. Dedicated Configuration Registers 26.3.4.3. Shared Pin MUX Registers 26.3.4.4. FPGA Access MUX Registers
26.3.5. Configuring HPS I/O Multiplexing x
26.3.5.1. Configuring Multiplexing at System Generation 26.3.5.2. Configuring Multiplexing at Boot Time
27. Introduction to the HPS Component x
27.1. MPU Subsystem 27.2. Arm* CoreSight* Debug Components 27.3. Interconnect 27.4. HPS-to-FPGA Interfaces 27.5. Memory Controllers 27.6. Support Peripherals 27.7. Interface Peripherals 27.8. On-Chip Memories
27.5. Memory Controllers x
27.5.1. HPS SDRAM Controller
27.5.1. HPS SDRAM Controller x
27.5.1.1. HMC and HPS Connectivity 27.5.1.2. Clocks 27.5.1.3. Resets
28. Instantiating the HPS Component x
28.1. Using the HPS Parameter Editor 28.2. FPGA Interfaces 28.3. Configuring HPS Clocks and Resets 28.4. Configuring Peripheral Pin Multiplexing 28.5. Configuring the External Memory Interface 28.6. Using the Address Span Extender Component 28.7. Generating and Compiling the HPS Component
28.2. FPGA Interfaces x
28.2.1. General Interfaces 28.2.2. FPGA-to-HPS SDRAM Interface 28.2.3. DMA Peripheral Request 28.2.4. Security Manager 28.2.5. Interrupts 28.2.6. AXI Bridges
28.3. Configuring HPS Clocks and Resets x
28.3.1. Alternate Clock Source from FPGA 28.3.2. User Clocks 28.3.3. Reset Interfaces 28.3.4. Peripheral FPGA Clocks
28.3.2. User Clocks x
28.3.2.1. User Clock Parameters 28.3.2.2. Clock Frequency Usage
28.4. Configuring Peripheral Pin Multiplexing x
28.4.1. Configuring Peripherals 28.4.2. Connecting Unassigned Pins to GPIO 28.4.3. Peripheral Signals Routed to FPGA
28.4.1. Configuring Peripherals x
28.4.1.1. Boot Source
29. HPS Component Interfaces x
29.1. Memory-Mapped Interfaces 29.2. Clocks 29.3. Resets 29.4. Debug and Trace Interfaces 29.5. Peripheral Signal Interfaces 29.6. Other Interfaces
29.1. Memory-Mapped Interfaces x
29.1.1. FPGA-to-HPS Bridge 29.1.2. HPS-to-FPGA and Lightweight HPS-to-FPGA Bridges 29.1.3. FPGA-to-HPS SDRAM Interface 29.1.4. EMIF Conduit
29.2. Clocks x
29.2.1. Alternative Clock Inputs to HPS PLLs 29.2.2. User Clocks 29.2.3. AXI Bridge FPGA Interface Clocks 29.2.4. SDRAM Clocks 29.2.5. Peripheral FPGA Clocks
29.3. Resets x
29.3.1. HPS-to-FPGA Reset Interfaces 29.3.2. HPS External Reset Request 29.3.3. Peripheral Reset Interfaces
29.4. Debug and Trace Interfaces x
29.4.1. FPGA System Trace Macrocell Events Interface 29.4.2. FPGA Cross Trigger Interface 29.4.3. Debug APB* Interface
29.5. Peripheral Signal Interfaces x
29.5.1. Platform Designer (Standard) Peripheral Port Interface Mapping 29.5.2. DMA Controller Interface
29.5.1. Platform Designer (Standard) Peripheral Port Interface Mapping x
29.5.1.1. NAND Flash Controller Interface 29.5.1.2. SD/MMC Controller Interface 29.5.1.3. Quad SPI Flash Controller Interface 29.5.1.4. Ethernet Media Access Controller Interface 29.5.1.5. USB 2.0 OTG Controller Interface 29.5.1.6. SPI Controller Interface 29.5.1.7. I2C Controller Interface 29.5.1.8. UART Interface
29.6. Other Interfaces x
29.6.1. MPU Standby and Event Interfaces 29.6.2. General Purpose Signals 29.6.3. FPGA-to-HPS Interrupts 29.6.4. Boot from FPGA Interface 29.6.5. Security Manager
30. Simulating the HPS Component x
30.1. Simulation Flows 30.2. Clock and Reset Interfaces 30.3. FPGA-to-HPS AXI Slave Interface 30.4. HPS-to-FPGA AXI Master Interface 30.5. Lightweight HPS-to-FPGA AXI Master Interface 30.6. HPS-to-FPGA MPU Event Interface 30.7. Interrupts Interface 30.8. HPS-to-FPGA Debug APB* Interface 30.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface 30.10. HPS-to-FPGA Cross-Trigger Interface 30.11. FPGA-to-HPS DMA Handshake Interface 30.12. Boot from FPGA Interface 30.13. Security Manager Anti-Tamper Signals Interface 30.14. EMIF Conduit 30.15. Pin MUX and Peripherals
30.1. Simulation Flows x
30.1.1. Setting Up the HPS Component for Simulation 30.1.2. Generating the HPS Simulation Model in Platform Designer (Standard) 30.1.3. Running the Simulations
30.1.1. Setting Up the HPS Component for Simulation x
30.1.1.1. HPS Conduit Interfaces Connecting to the FPGA
30.1.1.1. HPS Conduit Interfaces Connecting to the FPGA x
30.1.1.1.1. Setting Up the HPS Component for Simulation
30.1.3. Running the Simulations x
30.1.3.1. Running HPS RTL Simulation 30.1.3.2. Running HPS Post-Fit Simulation
30.1.3.2. Running HPS Post-Fit Simulation x
30.1.3.2.1. Post-Fit Simulation Files 30.1.3.2.2. BFM API Hierarchy Format
30.2. Clock and Reset Interfaces x
30.2.1. Clock Interface 30.2.2. Reset Interface
30.15. Pin MUX and Peripherals x
30.15.1. HPS Conduit Interfaces Connecting to the HPS I/O 30.15.2. HPS Conduit Interfaces Connecting to the FPGA
A. Booting and Configuration x
A.1. Boot Overview A.2. FPGA Configuration Overview A.3. Booting and Configuration Options A.4. Boot Definitions A.5. Boot ROM Flow A.6. Second-Stage Boot Flow A.7. FPGA Configuration A.8. FPGA Reconfiguration
A.4. Boot Definitions x
A.4.1. Reset A.4.2. Boot ROM A.4.3. Boot Select A.4.4. Flash Memory Devices for Booting A.4.5. Clock Select A.4.6. I/O Configuration A.4.7. L4 Watchdog 0 Timer A.4.8. Second-Stage Boot Loader A.4.9. Secure Boot
A.4.3. Boot Select x
A.4.3.1. Boot Source I/O Pins A.4.3.2. Boot Fuses
A.4.4. Flash Memory Devices for Booting x
A.4.4.1. SD/MMC Flash Devices A.4.4.2. NAND Flash Devices A.4.4.3. Quad SPI Flash Devices
A.4.4.1. SD/MMC Flash Devices x
A.4.4.1.1. Default Settings of the SD/MMC Controller A.4.4.1.2. CSEL Settings for the SD/MMC Controller
A.4.4.2. NAND Flash Devices x
A.4.4.2.1. NAND Flash Driver Features Supported in the Boot ROM Code A.4.4.2.2. CSEL Settings for the NAND Controller
A.4.4.3. Quad SPI Flash Devices x
A.4.4.3.1. Quad SPI Controller Default Settings A.4.4.3.2. Quad SPI Flash Delay Configuration A.4.4.3.3. Quad SPI Controller CSEL Settings
A.4.6. I/O Configuration x
A.4.6.1. I/O State
A.6. Second-Stage Boot Flow x
A.6.1. Typical Boot Flow (Non-Secure) A.6.2. Secure Boot Flow A.6.3. HPS State on Entry to the Second-Stage Boot Loader A.6.4. Loading the Second-Stage Boot Loader Image
A.7. FPGA Configuration x
A.7.1. Full FPGA Configuration Flow Through HPS A.7.2. Early I/O Release FPGA Configuration Flow Through HPS A.7.3. Arria 10 SoC FPGA Configuration Sequence Through FPGA Manager
A.7.2. Early I/O Release FPGA Configuration Flow Through HPS x
A.7.2.1. Handling an FPGA Configuration Failure after Early I/O Release
A.8. FPGA Reconfiguration x
A.8.1. Full FPGA Reconfiguration A.8.2. Arria 10 SoC FPGA Partial Reconfiguration Sequence Through FPGA Manager
1. Intel® Arria® 10 Hard Processor System Technical Reference Manual Revision History
2. Introduction to the Hard Processor System
3. Clock Manager
4. Reset Manager
5. FPGA Manager
6. System Manager
7. SoC Security
8. System Interconnect
9. HPS-FPGA Bridges
10. Cortex*-A9 Microprocessor Unit Subsystem
11. CoreSight* Debug and Trace
12. Error Checking and Correction Controller
13. On-Chip Memory
14. NAND Flash Controller
15. SD/MMC Controller
16. Quad SPI Flash Controller
17. DMA Controller
18. Ethernet Media Access Controller
19. USB 2.0 OTG Controller
20. SPI Controller
21. I2C Controller
22. UART Controller
23. General-Purpose I/O Interface
24. Timer
25. Watchdog Timer
26. Hard Processor System I/O Pin Multiplexing
27. Introduction to the HPS Component
28. Instantiating the HPS Component
29. HPS Component Interfaces
30. Simulating the HPS Component
A. Booting and Configuration

15.4. Functional Description of the SD/MMC Controller

This section describes the SD/MMC controller components and how the controller operates.

SD/MMC/CE-ATA Protocol

The SD/MMC/CE‑ATA protocol is based on command and data bit streams that are initiated by a start bit and terminated by a stop bit. Additionally, the SD/MMC controller provides a reference clock and is the only master interface that can initiate a transaction.†
  • Command—a token transmitted serially on the CMD pin that starts an operation.†
  • Response—a token from the card transmitted serially on the CMD pin in response to certain commands.†
  • Data—transferred serially using the data pins for data movement commands.†

In the following figure, the clock is a representative only and does not show the exact number of clock cycles.

Figure 65. Multiple–Block Read Operation†

The following figure illustrates an example of a command token sent by the host in a multiple‑block write operation.

Figure 66. Multiple‑–Block Write Operation†

BIU

The Bus Interface Unit (BIU) interfaces with the Card Interface Unit (CIU), and is connected to the level 3 (L3) interconnect and level 4 (L4) peripheral buses. The BIU consists of the following primary functional blocks, which are defined in the following sections:
  • Slave interface
  • Register block
  • FIFO buffer
  • Interrupt control
  • Internal DMA controller

Slave Interface

The host processor accesses the SD/MMC controller registers and data FIFO buffers through the slave interface.

Register Block

The register block is part of the BIU and provides read and write access to the CSRs.

All registers reside in the BIU clock domain, l4_mp_clk. When a command is sent to a card by setting the start command bit (start_cmd) of the command register (cmd) to 1, all relevant registers needed for the CIU operation are copied to the CIU block. During this time, software must not write to the registers that are transferred from the BIU to the CIU. The software must wait for the hardware to reset the start_cmd bit to 0 before writing to these registers again. The register unit has a hardware locking feature to prevent illegal writes to registers.

Registers Locked Out Pending Command Acceptance

After a command start is issued by setting the start_cmd bit of the cmd register, the following registers cannot be rewritten until the command is accepted by the CIU:†
  • Command (cmd)†
  • Command argument (cmdarg)†
  • Byte count (bytcnt)†
  • Block size (blksiz)†
  • Clock divider (clkdiv)†
  • Clock enable (clkena)†
  • Clock source (clksrc)†
  • Timeout (tmout)†
  • Card type (ctype)†

The hardware resets the start_cmd bit after the CIU accepts the command. If a host write to any of these registers is attempted during this locked time, the write is ignored and the hardware lock write error bit (hle) is set to 1 in the raw interrupt status register (rintsts). Additionally, if the interrupt is enabled and not masked for a hardware lock error, an interrupt is sent to the host.†

Once a command is accepted, you can send another command to the CIU—which has a one‑deep command queue—under the following conditions:†

  • If the previous command is not a data transfer command, the new command is sent to the SD/MMC/CE‑ATA card once the previous command completes.†
  • If the previous command is a data transfer command and if the wait previous data complete bit (wait_prvdata_complete) of the cmd register is set to 1 for the new command, the new command is sent to the SD/MMC/CE‑ATA card only when the data transfer completes.†
  • If the wait_prvdata_complete bit is 0, the new command is sent to the SD/MMC/CE‑ATA card as soon as the previous command is sent. Typically, use this feature to stop or abort a previous data transfer or query the card status in the middle of a data transfer.†

Interrupt Controller Unit

The interrupt controller unit generates an interrupt that depends on the rintsts register, the interrupt mask register (intmask), and the interrupt enable bit (int_enable) of the control register (ctrl). Once an interrupt condition is detected, the controller sets the corresponding interrupt bit in the rintsts register. The bit in the rintsts register remains set until the software clears the bit by writing a 1 to the interrupt bit; writing a 0 leaves the bit untouched.

The interrupt controller unit generates active high, level sensitive interrupts that are asserted only when at least one bit in the rintsts register is set to 1, the corresponding intmask register bit is 1, and the int_enable bit of the ctrl register is 1.

The int_enable bit of the ctrl register is cleared during a power-on reset, and the intmask register bits are set to 0x0000000, which masks all the interrupts.

Table 139.  Interrupt Status Register Bits†
Bits Interrupt Description
16 SDIO Interrupts† Interrupts from SDIO cards.†
15 End Bit Error (read)/Write no CRC (EBE)†

Error in end-bit during read operation, or no data CRC received during write operation.†

Note: For MMC CMD19, there may be no CRC status returned by the card. Hence, EBE is set for CMD19. The application should not treat this as an error. †
14 Auto Command Done (ACD)†

Stop/abort commands automatically sent by card unit and not initiated by host; similar to Command Done (CD) interrupt. †

Recommendation: Software typically need not enable this for non CE-ATA accesses; Data Transfer Over (DTO) interrupt that comes after this interrupt determines whether data transfer has correctly competed. For CE-ATA accesses, if the software sets send_auto_stop_ccsd bit in the control register, then software should enable this bit.†

13 Start Bit Error (SBE)

Error in data start bit when data is read from a card. In 4-bit mode, if all data bits do not have start bit, then this error is set.

12 Hardware Locked write Error (HLE)† During hardware-lock period, write attempted to one of locked registers. †
11 FIFO Underrun/Overrun Error (FRUN)†

Host tried to push data when FIFO was full, or host tried to read data when FIFO was empty. Typically this should not happen, except due to error in software. †

Card unit never pushes data into FIFO when FIFO is full, and pop data when FIFO is empty. †

If IDMAC (Internal Direct Memory Access Controller) is enabled, FIFO underrun/overrun can occur due to a programming error on MSIZE and watermark values in FIFOTH register; for more information, refer to Internal Direct Memory Access Controller (IDMAC) section in the "Synopsys DesignWare Cores Mobile Storage Host Databook".†

10 Data Starvation by Host Timeout (HTO)†

To avoid data loss, card clock out (cclk_out) is stopped if FIFO is empty when writing to card, or FIFO is full when reading from card. Whenever card clock is stopped to avoid data loss, data-starvation timeout counter is started with data-timeout value. This interrupt is set if host does not fill data into FIFO during write to card, or does not read from FIFO during read from card before timeout period. †

Even after timeout, card clock stays in stopped state, with CIU state machines waiting. It is responsibility of host to push or pop data into FIFO upon interrupt, which automatically restarts cclk_out and card state machines. †

Even if host wants to send stop/abort command, it still must ensure to push or pop FIFO so that clock starts in order for stop/abort command to send on cmd signal along with data that is sent or received on data line. †

9 Data Read Timeout (DRTO)/Boot Data Start (BDS)†
  • In Normal functioning mode: Data read timeout (DRTO) Data timeout occurred. Data Transfer Over (DTO) also set if data timeout occurs. †
  • In Boot Mode: Boot Data Start (BDS) When set, indicates that SD/MMC controller has started to receive boot data from the card. A write to this register with a value of 1 clears this interrupt.†
8 Response Timeout (RTO)/ Boot Ack Received (BAR)†
  • In Normal functioning mode: Response timeout (RTO) Response timeout occurred. Command Done (CD) also set if response timeout occurs. If command involves data transfer and when response times out, no data transfer is attempted by SD/MMC controller.†
  • In Boot Mode: Boot Ack Received (BAR) When expect_boot_ack is set, on reception of a boot acknowledge pattern—0-1-0—this interrupt is asserted. A write to this register with a value of 1 clears this interrupt.†
7 Data CRC Error (DCRC)†

Received Data CRC does not match with locally-generated CRC in CIU; expected when a negative CRC is received. †

6 Response CRC Error (RCRC)†

Response CRC does not match with locally-generated CRC in CIU.†

5 Receive FIFO Data Request (RXDR)†

Interrupt set during read operation from card when FIFO level is greater than Receive-Threshold level.†

Recommendation: In DMA modes, this interrupt should not be enabled.†

ISR, in non-DMA mode: 
pop RX_WMark + 1 data from FIFO
†
4 Transmit FIFO Data Request (TXDR)†

Interrupt set during write operation to card when FIFO level reaches less than or equal to Transmit-Threshold level.†

Recommendation: In DMA modes, this interrupt should not be enabled.†

ISR in non-DMA mode: † 

   if (pending_bytes > \†
   (FIFO_DEPTH - TX_WMark))†
        push (FIFO_DEPTH - \†
        TX_WMark) data into FIFO†
   else†
        push pending_bytes data \†
        into FIFO†
3 Data Transfer (DTO)†

Data transfer completed, even if there is Start Bit Error or CRC error. This bit is also set when “read data-timeout” occurs or CCS is sampled from CE-ATA device.†

Recommendation: In non-DMA mode, when data is read from card, on seeing interrupt, host should read any pending data from FIFO. In DMA mode, DMA controllers guarantee FIFO is flushed before interrupt.†

Note: DTO bit is set at the end of the last data block, even if the device asserts MMC busy after the last data block.†
2 Command Done (CD)†

Command sent to card and received response from card, even if Response Error or CRC error occurs. Also set when response timeout occurs or CCSD sent to CE-ATA device.†

1 Response Error (RE)†

Error in received response set if one of following occurs:†

  • Transmission bit != 0†
  • Command index mismatch†
  • End-bit != 1†
0 Card-Detect (CDT)†

When one or more cards inserted or removed, this interrupt occurs. Software should read card-detect register (CDETECT, 0x50) to determine current card status.†

Recommendation: After power-on and before enabling interrupts, software should read card detect register and store it in memory. When interrupt occurs, it should read card detect register and compare it with value stored in memory to determine which card(s) were removed/inserted. Before exiting ISR, software should update memory with new card-detect value.†

Interrupt Setting and Clearing

The SDIO Interrupts, Receive FIFO Data Request, and Transmit FIFO Data Request interrupts are set by level‑sensitive interrupt sources. Therefore, the interrupt source must be first cleared before you can reset the interrupt’s corresponding bit in the rintsts register to 0.†

For example, on receiving the Receive FIFO Data Request interrupt, the FIFO buffer must be emptied so that the FIFO buffer count is not greater than the RX watermark, which causes the interrupt to be triggered.†

The rest of the interrupts are triggered by single clock‑pulse‑width sources.†

FIFO Buffer

The SD/MMC controller has a 4 KB data FIFO buffer for storing transmit and receive data.

The FIFO has an ECC controller built-in to provide ECC protection. The ECC controller is able to detect single-bit and double-bit errors, and correct the single-bit errors. The ECC operation and functionality is programmable through the ECC register slave interface. The ECC register slave interface provides host access to configure the ECC logic as well as inject bit errors into the memory. It also provides the host access to memory initialization hardware used to clear out the memory contents including the ECC bits. The ECC controller generates interrupts upon occurrences of single- and double-bit errors, and the interrupt signals are connected to the system manager.

Note: Since SD/MMC has multiple memories, it must initialize both memories explicitly. Initialization is controlled by software through the ECC Control (CTRL) register. This process cannot be interrupted or stopped once it starts; hence software must wait for the initialization complete bit to be set in the Initialization Status (INITSTAT) register. Memory accesses are allowed after the initialization process is complete.

Internal DMA Controller

Internal DMA controller ( AHB* Master) enables the core to act as a Master on the AHB* to transfer data to and from the AHB* .
  • Supports 32-bit data
  • Supports split, retry, and error AHB* responses, but does not support wrap
  • Configurable for little-endian or big-endian mode
  • Allows the selection of AHB* burst type through software

The internal DMA controller has a CSR and a single transmit or receive engine, which transfers data from system memory to the card and vice versa. The controller uses a descriptor mechanism to efficiently move data from source to destination with minimal host processor intervention. You can configure the controller to interrupt the host processor in situations such as transmit and receive data transfer completion from the card, as well as other normal or error conditions. The DMA controller and the host driver communicate through a single data structure.†

The internal DMA controller transfers the data received from the card to the data buffer in the system memory, and transfers transmit data from the data buffer in the memory to the controller’s FIFO buffer. Descriptors that reside in the system memory act as pointers to these buffers.†

A data buffer resides in the physical memory space of the system memory and consists of complete or partial data. The buffer status is maintained in the descriptor. Data chaining refers to data that spans multiple data buffers. However, a single descriptor cannot span multiple data buffers.†

A single descriptor is used for both reception and transmission. The base address of the list is written into the descriptor list base address register (dbaddr). A descriptor list is forward linked. The last descriptor can point back to the first entry to create a ring structure. The descriptor list resides in the physical memory address space of the host. Each descriptor can point to a maximum of two data buffers.†

Internal DMA Controller Descriptors

The internal DMA controller uses these types of descriptor structures:†
  • Dual‑buffer structure—The distance between two descriptors is determined by the skip length value written to the descriptor skip length field (dsl) of the bus mode register (bmod).†
Figure 67. Dual‑Buffer Descriptor Structure†
  • Chain structure—Each descriptor points to a unique buffer, and to the next descriptor in a linked list.†
Figure 68. Chain Descriptor Structure†

Internal DMA Controller Descriptor Address

The descriptor address must be aligned to the 32‑bit bus. Each descriptor contains 16 bytes of control and status information.†

Table 140.  Descriptor Format
Name Off- set 31 30 29:27 26 25:14 13 12:7 6 5 4 3 2 1 0
DES0 0 OWN CES — ER CH FS LD DIC —
DES1 4 — BS2 BS1
DES2 8 BAP1
DES3 12 BAP2 or Next Descriptor Address

Internal DMA Controller Descriptor Fields

The DES0 field in the internal DMA controller descriptor contains control and status information.

Table 141.  Internal DMA Controller DES0 Descriptor Field†
Bits Name Description

31

OWN

When set to 1, this bit indicates that the descriptor is owned by the internal DMA controller.

When this bit is set to 0, it indicates that the descriptor is owned by the host. The internal DMA controller resets this bit to 0 when it completes the data transfer.

30

Card Error Summary (CES)

The CES bit indicates whether a transaction error occurred. The CES bit is the logical OR of the following error bits in the rintsts register.

  • End‑bit error (ebe)
  • Response timeout (rto)
  • Response CRC (rcrc)
  • Start‑bit error (sbe)
  • Data read timeout (drto)
  • Data CRC for receive (dcrc)
  • Response error (re)

29:6

Reserved

—

5

End of Ring (ER)

When set to 1, this bit indicates that the descriptor list reached its final descriptor. The internal DMA controller returns to the base address of the list, creating a descriptor ring. ER is meaningful for only a dual‑buffer descriptor structure.

4

Second Address Chained (CH)

When set to 1, this bit indicates that the second address in the descriptor is the next descriptor address rather than the second buffer address. When this bit is set to 1, BS2 (DES1[25:13]) must be all zeros.

3

First Descriptor (FD)

When set to 1, this bit indicates that this descriptor contains the first buffer of the data. If the size of the first buffer is 0, next descriptor contains the beginning of the data.

2

Last Descriptor (LD)

When set to 1, this bit indicates that the buffers pointed to by this descriptor are the last buffers of the data.

1

Disable Interrupt on Completion (DIC)

When set to 1, this bit prevents the setting of the TI/RI bit of the internal DMA controller status register (idsts) for the data that ends in the buffer pointed to by this descriptor.

0

Reserved

—

Table 142.  Internal DMA Controller DES1 Descriptor Field† The DES1 descriptor field contains the buffer size.
Bits Name Description

31:26

Reserved

—

25:13

Buffer 2 Size (BS2)

This field indicates the second data buffer byte size. The buffer size must be a multiple of four. When the buffer size is not a multiple of four, the resulting behavior is undefined. This field is not valid if DES0[4] is set to 1.

12:0

Buffer 1 Size (BS1)

Indicates the data buffer byte size, which must be a multiple of four bytes. When the buffer size is not a multiple of four, the resulting behavior is undefined. If this field is 0, the DMA ignores the buffer and proceeds to the next descriptor for a chain structure, or to the next buffer for a dual‑buffer structure.

If there is only one descriptor and only one buffer to be programmed, you need to use only buffer 1 and not buffer 2.

Table 143.  Internal DMA Controller DES2 Descriptor Field† The DES2 descriptor field contains the address pointer to the data buffer.
Bits Name Description

31:0

Buffer Address Pointer 1 (BAP1)

These bits indicate the physical address of the first data buffer. The internal DMA controller ignores DES2 [1:0], because it only performs 32‑bit aligned accesses.

Table 144.  Internal DMA Controller DES3 Descriptor Field† The DES3 descriptor field contains the address pointer to the next descriptor if the present descriptor is not the last descriptor in a chained descriptor structure or the second buffer address for a dual‑buffer structure.†
Bits Name Description

31:0

Buffer Address Pointer 2 (BAP2) or Next Descriptor Address

These bits indicate the physical address of the second buffer when the dual‑buffer structure is used. If the Second Address Chained (DES0[4]) bit is set to 1, this address contains the pointer to the physical memory where the next descriptor is present.

If this is not the last descriptor, the next descriptor address pointer must be aligned to 32 bits. Bits 1 and 0 are ignored.

Host Bus Burst Access

The internal DMA controller attempts to issue fixed‑length burst transfers on the master interface if configured using the fixed burst bit (fb) of the bmod register. The maximum burst length is indicated and limited by the programmable burst length (pbl) field of the bmod register. When descriptors are being fetched, the master interface always presents a burst size of four to the interconnect.†

The internal DMA controller initiates a data transfer only when sufficient space to accommodate the configured burst is available in the FIFO buffer or the number of bytes to the end of transfer is less than the configured burst‑length. When the DMA master interface is configured for fixed‑length bursts, it transfers data using the most efficient combination of INCR4, INCR8 or INCR16 and SINGLE transactions. If the DMA master interface is not configured for fixed length bursts, it transfers data using INCR (undefined length) and SINGLE transactions.†

Host Data Buffer Alignment

The transmit and receive data buffers in system memory must be aligned to a 32‑bit boundary.

Buffer Size Calculations

The driver knows the amount of data to transmit or receive. For transmitting to the card, the internal DMA controller transfers the exact number of bytes from the FIFO buffer, indicated by the buffer size field of the DES1 descriptor field.†

If a descriptor is not marked as last (with the LD bit of the DES0 field set to 0) then the corresponding buffer(s) of the descriptor are considered full, and the amount of valid data in a buffer is accurately indicated by its buffer size field. If a descriptor is marked as last, the buffer might or might not be full, as indicated by the buffer size in the DES1 field. The driver is aware of the number of locations that are valid.† The driver is expected to ignore the remaining, invalid bytes.

Internal DMA Controller Interrupts

Interrupts can be generated as a result of various events. The idsts register contains all the bits that might cause an interrupt. The internal DMA controller interrupt enable register (idinten) contains an enable bit for each of the events that can cause an interrupt to occur.†

There are two summary interrupts—the normal interrupt summary bit (nis) and the abnormal interrupt summary bit (ais)—in the idsts register.† The nis bit results from a logical OR of the transmit interrupt (ti) and receive interrupt (ri) bits in the idsts register. The ais bit is a logical OR result of the fatal bus error interrupt (fbe), descriptor unavailable interrupt (du), and card error summary interrupt (ces) bits in the idsts register.

Interrupts are cleared by writing a 1 to the corresponding bit position.† If a 0 is written to an interrupt’s bit position, the write is ignored, and does not clear the interrupt. When all the enabled interrupts within a group are cleared, the corresponding summary bit is set to 0. When both the summary bits are set to 0, the interrupt signal is de‑asserted.†

Interrupts are not queued. If another interrupt event occurs before the driver has responded to the previous interrupt, no additional interrupts are generated. For example, the ri bit of the idsts register indicates that one or more data has been transferred to the host buffer.†

An interrupt is generated only once for simultaneous, multiple events. The driver must scan the idsts register for the interrupt cause.† The final interrupt signal from the controller is a logical OR of the interrupts from the BIU and internal DMA controller.

Internal DMA Controller Functional State Machine†

The following list explains each state of the functional state machine:†

  1. The internal DMA controller performs four accesses to fetch a descriptor.†
  2. The DMA controller stores the descriptor information internally. If it is the first descriptor, the controller issues a FIFO buffer reset and waits until the reset is complete.†
  3. The internal DMA controller checks each bit of the descriptor for the correctness. If bit mismatches are found, the appropriate error bit is set to 1 and the descriptor is closed by setting the OWN bit in the DES0 field to 1.†

    The rintsts register indicates one of the following conditions:†

    • Response timeout†
    • Response CRC error†
    • Data receive timeout†
    • Response error†
  4. The DMA waits for the RX watermark to be reached before writing data to system memory, or the TX watermark to be reached before reading data from system memory. The RX watermark represents the number of bytes to be locally stored in the FIFO buffer before the DMA writes to memory. The TX watermark represents the number of free bytes in the local FIFO buffer before the DMA reads data from memory.†
  5. If the value of the programmable burst length (PBL) field is larger than the remaining amount of data in the buffer, single transfers are initiated. If dual buffers are being used, and the second buffer contains no data (buffer size = 0), the buffer is skipped and the descriptor is closed.†
  6. The OWN bit in descriptor is set to 0 by the internal DMA controller after the data transfer for one descriptor is completed. If the transfer spans more than one descriptor, the DMA controller fetches the next descriptor. If the transfer ends with the current descriptor, the internal DMA controller goes to idle state after setting the ri bit or the ti bit of the idsts register. Depending on the descriptor structure (dual buffer or chained), the appropriate starting address of descriptor is loaded. If it is the second data buffer of dual buffer descriptor, the descriptor is not fetched again.†

Abort During Internal DMA Transfer

If the host issues an SD/SDIO STOP_TRANSMISSION command (CMD12) to the card while data transfer is in progress, the internal DMA controller closes the present descriptor after completing the data transfer until a Data Transfer Over (DTO) interrupt is asserted. Once a STOP_TRANSMISSION command is issued, the DMA controller performs single burst transfers.†
  • For a card write operation, the internal DMA controller keeps writing data to the FIFO buffer after fetching it from the system memory until a DTO interrupt is asserted. This is done to keep the card clock running so that the STOP_TRANSMISSION command is reliably sent to the card.†
  • For a card read operation, the internal DMA controller keeps reading data from the FIFO buffer and writes to the system memory until a DTO interrupt is generated. This is required because DTO interrupt is not generated until and unless all the FIFO buffer data is emptied.†
Note: For a card write abort, only the current descriptor during which a STOP_TRANSMISSION command is issued is closed by the internal DMA controller. The remaining unread descriptors are not closed by the internal DMA controller.†
Note: For a card read abort, the internal DMA controller reads the data out of the FIFO buffer and writes them to the corresponding descriptor data buffers. The remaining unread descriptors are not closed.†

Fatal Bus Error Scenarios

A fatal bus error occurs when the master interface issues an error response. This error is a system error, so the software driver must not perform any further setup on the controller. The only recovery mechanism from such scenarios is to perform one of the following tasks:†
  • Issue a reset to the controller through the reset manager.†
  • Issue a program controller reset by writing to the controller reset bit (controller_reset) of the ctrl register.†

FIFO Buffer Overflow and Underflow

During normal data transfer conditions, FIFO buffer overflow and underflow does not occur. However, if there is a programming error, a FIFO buffer overflow or underflow can result. For example, consider the following scenarios.†

For transmit:†

  • PBL=4†
  • TX watermark = 1†

For these programming values, if the FIFO buffer has only one location empty, the DMA attempts to read four words from memory even though there is only one word of storage available. This results in a FIFO Buffer Overflow interrupt.†

For receive:†

  • PBL=4†
  • RX watermark = 1†

For these programming values, if the FIFO buffer has only one location filled, the DMA attempts to write four words, even though only one word is available. This results in a FIFO Buffer Underflow interrupt.†

The driver must ensure that the number of bytes to be transferred, as indicated in the descriptor, is a multiple of four bytes. For example, if the bytcnt register = 13, the number of bytes indicated in the descriptor must be rounded up to 16 because the length field must always be a multiple of four bytes.†

PBL and Watermark Levels

This table shows legal PBL and FIFO buffer watermark values for internal DMA controller data transfer operations.†

Table 145.  PBL and Watermark Levels†
PBL (Number of transfers) TX/RX FIFO Buffer Watermark Value

1

greater than or equal to 1

4

greater than or equal to 4

8

greater than or equal to 8

16

greater than or equal to 16

32

greater than or equal to 32

64

greater than or equal to 64

128

greater than or equal to 128

256

greater than or equal to 256

CIU

The Card Interface Unit (CIU) interfaces with the BIU and SD/MMC cards or devices. The host processor writes command parameters to the SD/MMC controller’s BIU control registers and these parameters are then passed to the CIU. Depending on control register values, the CIU generates SD/MMC command and data traffic on the card bus according to the SD/MMC protocol. The control register values also decide whether the command and data traffic is directed to the CE‑ATA card, and the SD/MMC controller controls the command and data path accordingly.†

The following list describes the CIU operation restrictions:†

  • After a command is issued, the CIU accepts another command only to check read status or to stop the transfer.†
  • Only one data transfer command can be issued at a time.†
  • During an open‑ended card write operation, if the card clock is stopped because the FIFO buffer is empty, the software must first fill the data into the FIFO buffer and start the card clock. It can then issue only an SD/SDIO STOP_TRANSMISSION (CMD12) command to the card.†
  • During an SDIO/COMBO card transfer, if the card function is suspended and the software wants to resume the suspended transfer, it must first reset the FIFO buffer and start the resume command as if it were a new data transfer command.†
  • When issuing SD/SDIO card reset commands (GO_IDLE_STATE, GO_INACTIVE_STATE or CMD52_reset) while a card data transfer is in progress, the software must set the stop abort command bit (stop_abort_cmd) in the cmd register to 1 so that the controller can stop the data transfer after issuing the card reset command.†
  • If the card clock is stopped because the FIFO buffer is full during a card read, the software must read at least two FIFO buffer locations to start the card clock.†
  • If CE‑ATA card device interrupts are enabled (the nIEN bit is set to 0 in the ATA control register), a new RW_BLK command must not be sent to the same card device if there is a pending RW_BLK command in progress (the RW_BLK command used in this document is the RW_MULTIPLE_BLOCK MMC command defined by the CE‑ATA specification). Only the Command Completion Signal Disable (CCSD) command can be sent while waiting for the Command Completion Signal (CCS).†
  • For the same card device, a new command is allowed for reading status information, if interrupts are disabled in the CE‑ATA card (the nIEN bit is set to 1 in the ATA control register).†
  • Open‑ended transfers are not supported for the CE‑ATA card devices.†
  • The send_auto_stop signal is not supported (software must not set the send_auto_stop bit in the cmd register) for CE‑ATA transfers.†

The CIU consists of the following primary functional blocks:†

  • Command path†
  • Data path†
  • Clock control†

Command Path

The command path performs the following functions:†
  • Load card command parameters†
  • Send commands to card bus†
  • Receive responses from card bus†
  • Send responses to BIU†
  • Load clock parameters†
  • Drives the P‑bit on command pin†

A new command is issued to the controller by writing to the BIU registers and setting the start_cmd bit in the cmd register. The command path loads the new command (command, command argument, timeout) and sends an acknowledgement to the BIU.†

After the new command is loaded, the command path state machine sends a command to the card bus—including the internally generated seven‑term CRC (CRC‑7)—and receives a response, if any. The state machine then sends the received response and signals to the BIU that the command is done, and then waits for eight clock cycles before loading a new command. In CE‑ATA data payload transfer (RW_MULTIPLE_BLOCK) commands, if the card device interrupts are enabled (the nIEN bit is set to 0 in the ATA control register), the state machine performs the following actions after receiving the response:†

  • Does not drive the P‑bit; it waits for CCS, decodes and goes back to idle state, and then drives the P‑bit.†
  • If the host wants to send the CCSD command and if eight clock cycles are expired after the response, it sends the CCSD pattern on the command pin.†

Load Command Parameters

Commands or responses are loaded in the command path in the following situations:†
  • New command from BIU—When the BIU sends a new command to the CIU, the start_cmd bit is set to 1 in the cmd register.†
  • Internally‑generated send_auto_stop—When the data path ends, the SD/SDIO STOP command request is loaded.†
  • Interrupt request (IRQ) response with relative card address (RCA) 0x000—When the command path is waiting for an IRQ response from the MMC and a “send irq response” request is signaled by the BIU, the send IRQ request bit (send_irq_response) is set to 1 in the ctrl register.†

Loading a new command from the BIU in the command path depends on the following cmd register bit settings:†

  • update_clock_registers_only—If this bit is set to 1 in the cmd register, the command path updates only the clkena, clkdiv, and clksrc registers. If this bit is set to 0, the command path loads the cmd, cmdarg, and tmout registers. It then processes the new command, which is sent to the card.†
  • wait_prvdata_complete—If this bit is set to 1, the command path loads the new command under one of the following conditions:†
    • Immediately, if the data path is free (that is, there is no data transfer in progress), or if an open‑ended data transfer is in progress (bytcnt = 0).†
    • After completion of the current data transfer, if a predefined data transfer is in progress.†

Send Command and Receive Response

After a new command is loaded in the command path (the update_clock_registers_only bit in the cmd register is set to 0), the command path state machine sends out a command on the card bus.†
Figure 69.  Command Path State Machine†

The command path state machine performs the following functions, according to cmd register bit values:†

  1. send_initialization—Initialization sequence of 80 clock cycles is sent before sending the command.†
  2. response_expected—A response is expected for the command. After the command is sent out, the command path state machine receives a 48‑bit or 136‑bit response and sends it to the BIU. If the start bit of the card response is not received within the number of clock cycles (as set up in the tmout register), the rto bit and command done (CD) bit are set to 1 in the rintsts register, to signal to the BIU. If the response‑expected bit is set to 0, the command path sends out a command and signals a response done to the BIU, which causes the cmd bit to be set to 1 in the rintsts register.†
  3. response_length—If this bit is set to 1, a 136‑bit long response is received; if it is set to 0, a 48‑bit short response is received.†
  4. check_response_crc—If this bit is set to 1, the command path compares CRC‑7 received in the response with the internally‑generated CRC‑7. If the two do not match, the response CRC error is signaled to the BIU, that is, the rcrc bit is set to 1 in the rintsts register.†

Send Response to BIU

If the response_expected bit is set to 1 in the cmd register, the received response is sent to the BIU. Response register 0 (resp0) is updated for a short response, and the response register 3 (resp3), response register 2 (resp2), response register 1 (resp1), and resp0 registers are updated on a long response, after which the cmd bit is set to 1 in the rintsts register. If the response is for an AUTO_STOP command sent by the CIU, the response is written to the resp1 register, after which the auto command done bit (acd) is set to 1 in the rintsts register.†

The command path verifies the contents of the card response.

Table 146.  Card Response Fields†
Field Contents

Response transmission bit

0

Command index

Command index of the sent command

End bit

1

The command index is not checked for a 136‑bit response or if the check_response_crc bit in the cmd register is set to 0. For a 136‑bit response and reserved CRC 48‑bit responses, the command index is reserved, that is, 0b111111.†

Driving P-bit to the CMD Pin

The command path drives a one‑cycle pull‑up bit (P‑bit) to 1 on the CMD pin between two commands if a response is not expected. If a response is expected, the P‑bit is driven after the response is received and before the start of the next command. While accessing a CE‑ATA card device, for commands that expect a CCS, the P‑bit is driven after the response only if the interrupts are disabled in the CE‑ATA card (the nIEN bit is set to 1 in the ATA control register), that is, the CCS expected bit (ccs_expected) in the cmd register is set to 0. If the command expects the CCS, the P‑bit is driven only after receiving the CCS.†

Polling the CCS

CE‑ATA card devices generate the CCS to notify the host controller of the normal ATA command completion or ATA command termination. After receiving the response from the card, the command path state machine performs the functions illustrated in the following figure according to cmd register bit values.†
Figure 70. CE‑ATA Command Path State Machine†

The above figure illustrates:

  • Response end bit state—The state machine receives the end bit of the response from the card device. If the ccs_expected bit of the cmd register is set to 1, the state machine enters the wait CCS state.†
  • Wait CCS—The state machine waits for the CCS from the CE‑ATA card device. While waiting for the CCS, the following events can happen:†
    1. Software sets the send CCSD bit (send_ccsd) in the ctrl register, indicating not to wait for CCS and to send the CCSD pattern on the command line.†
    2. Receive the CCS on the CMD line.†
  • Send CCSD command—Sends the CCSD pattern (0b00001) on the CMD line.†

CCS Detection and Interrupt to Host Processor

If the ccs_expected bit in the cmd register is set to 1, the CCS from the CE‑ATA card device is indicated by setting the data transfer over bit (dto) in the rintsts register. The controller generates a DTO interrupt if this interrupt is not masked.†

For the RW_MULTIPLE_BLOCK commands, if the CE‑ATA card device interrupts are disabled (the nIEN bit is set to 1 in the ATA control register)— that is, the ccs_expected bit is set to 0 in the cmd register—there are no CCSs from the card. When the data transfer is over—that is, when the requested number of bytes are transferred—the dto bit in the rintsts register is set to 1.†

CCS Timeout

If the command expects a CCS from the card device (the ccs_expected bit is set to 1 in the cmd register), the command state machine waits for the CCS and remains in the wait CCS state. If the CE‑ATA card fails to send out the CCS, the host software must implement a timeout mechanism to free the command and data path. The controller does not implement a hardware timer; it is the responsibility of the host software to maintain a software timer.†

In the event of a CCS timeout, the host must issue a CCSD command by setting the send_ccsd bit in the ctrl register. The controller command path state machine sends the CCSD command to the CE‑ATA card device and exits to an idle state. After sending the CCSD command, the host must also send an SD/SDIO STOP_TRANSMISSION command to the CE‑ATA card to abort the outstanding ATA command.†

Send CCSD Command

If the send_ccsd bit in the ctrl register is set to 1, the controller sends a CCSD pattern on the CMD line. The host can send the CCSD command while waiting for the CCS or after a CCS timeout happens.†

After sending the CCSD pattern, the controller sets the cmd bit in the rintsts register and also generates an interrupt to the host if the Command Done interrupt is not masked.†

Note: Within the CIU block, if the send_ccsd bit in the ctrl register is set to 1 on the same clock cycle as CCS is sampled, the CIU block does not send a CCSD pattern on the CMD line. In this case, the dto and cmd bits in the rintsts register are set to 1.†
Note: Due to asynchronous boundaries, the CCS might have already happened and the send_ccsd bit is set to 1. In this case, the CCSD command does not go to the CE‑ATA card device and the send_ccsd bit is not set to 0. The host must reset the send_ccsd bit to 0 before the next command is issued.†

If the send auto stop CCSD (send_auto_stop_ccsd) bit in the ctrl register is set to 1, the controller sends an internally generated STOP_TRANSMISSION command (CMD12) after sending the CCSD pattern. The controller sets the acd bit in the rintsts register.†

I/O transmission delay (NACIO Timeout)

The host software maintains the timeout mechanism for handling the I/O transmission delay (NACIO cycles) time‑outs while reading from the CE‑ATA card device. The controller neither maintains any timeout mechanism nor indicates that NACIO cycles are elapsed while waiting for the start bit of a data token. The I/O transmission delay is applicable for read transfers using the RW_REG and RW_BLK commands; the RW_REG and RW_BLK commands used in this document refer to the RW_MULTIPLE_REGISTER and RW_MULTIPLE_BLOCK MMC commands defined by the CE‑ATA specification.†
Note: After the NACIO timeout, the application must abort the command by sending the CCSD and STOP commands, or the STOP command. The Data Read Timeout (DRTO) interrupt might be set to 1 while a STOP_TRANSMISSION command is transmitted out of the controller, in which case the data read timeout boot data start bit (bds) and the dto bit in the rintsts register are set to 1.†

Data Path

The data path block reads the data FIFO buffer and transmits data on the card bus during a write data transfer, or receives data and writes it to the FIFO buffer during a read data transfer. The data path loads new data parameters—data expected, read/write data transfer, stream/block transfer, block size, byte count, card type, timeout registers—whenever a data transfer command is not in progress. If the data transfer expected bit (data_expected) in the cmd register is set to 1, the new command is a data transfer command and the data path starts one of the following actions:†
  • Transmits data if the read/write bit = 1†
  • Receives data if read/write bit = 0†

Data Transmit

The data transmit state machine starts data transmission two clock cycles after a response for the data write command is received. This occurs even if the command path detects a response error or response CRC error. If a response is not received from the card because of a response timeout, data is not transmitted. Depending upon the value of the transfer mode bit (transfer_mode) in the cmd register, the data transmit state machine puts data on the card data bus in a stream or in blocks.†
Figure 71. Data Transmit State Machine†
Stream Data Transmit
If the transfer_mode bit in the cmd register is set to 1, the transfer is a stream‑write data transfer. The data path reads data from the FIFO buffer from the BIU and transmits in a stream to the card data bus. If the FIFO buffer becomes empty, the card clock is stopped and restarted once data is available in the FIFO buffer.†

If the bytcnt register is reset to 0, the transfer is an open‑ended stream‑write data transfer. During this data transfer, the data path continuously transmits data in a stream until the host software issues an SD/SDIO STOP command. A stream data transfer is terminated when the end bit of the STOP command and end bit of the data match over two clock cycles.†

If the bytcnt register is written with a nonzero value and the send_auto_stop bit in the cmd register is set to 1, the STOP command is internally generated and loaded in the command path when the end bit of the STOP command occurs after the last byte of the stream write transfer matches. This data transfer can also terminate if the host issues a STOP command before all the data bytes are transferred to the card bus.†

Single Block Data
If the transfer_mode bit in the cmd register is set to 0 and the bytcnt register value is equal to the value of the block_size register, a single‑block write‑data transfer occurs. The data transmit state machine sends data in a single block, where the number of bytes equals the block size, including the internally‑generated 16‑term CRC (CRC‑16).†

If the ctype register is set for a 1‑bit, 4‑bit, or 8‑bit data transfer, the data is transmitted on 1, 4, or 8 data lines, respectively, and CRC‑16 is separately generated and transmitted for 1, 4, or 8 data lines, respectively.†

After a single data block is transmitted, the data transmit state machine receives the CRC status from the card and signals a data transfer to the BIU. This happens when the dto bit in the rintsts register is set to 1.†

If a negative CRC status is received from the card, the data path signals a data CRC error to the BIU by setting the dcrc bit in the rintsts register.†

Additionally, if the start bit of the CRC status is not received by two clock cycles after the end of the data block, a CRC status start‑bit error (SBE) is signaled to the BIU by setting the sbe bit in the rintsts register.†

Multiple Block Data
A multiple‑block write‑data transfer occurs if the transfer_mode bit in the cmd register is set to 0 and the value in the bytcnt register is not equal to the value of the block_size register. The data transmit state machine sends data in blocks, where the number of bytes in a block equals the block size, including the internally‑generated CRC‑16 value.†

If the ctype register is set to 1‑bit, 4‑bit, or 8‑bit data transfer, the data is transmitted on 1-, 4-, or 8-data lines, respectively, and CRC‑16 is separately generated and transmitted on 1-, 4-, or 8-data lines, respectively.†

After one data block is transmitted, the data transmit state machine receives the CRC status from the card. If the remaining byte count becomes 0, the data path signals to the BIU that the data transfer is done. This happens when the dto bit in the rintsts register is set to 1.†

If the remaining data bytes are greater than zero, the data path state machine starts to transmit another data block.†

If a negative CRC status is received from the card, the data path signals a data CRC error to the BIU by setting the dcrc bit in the rintsts register, and continues further data transmission until all the bytes are transmitted.†

If the CRC status start bit is not received by two clock cycles after the end of a data block, a CRC status SBE is signaled to the BIU by setting the ebe bit in the rintsts register and further data transfer is terminated.†

If the send_auto_stop bit is set to 1 in the cmd register, the SD/SDIO STOP command is internally generated during the transfer of the last data block, where no extra bytes are transferred to the card. The end bit of the STOP command might not exactly match the end bit of the CRC status in the last data block.†

If the block size is less than 4, 16, or 32 for card data widths of 1 bit, 4 bits, or 8 bits, respectively, the data transmit state machine terminates the data transfer when all the data is transferred, at which time the internally-generated STOP command is loaded in the command path.†

If the bytcnt is zero (the block size must be greater than zero) the transfer is an open‑ended block transfer. The data transmit state machine for this type of data transfer continues the block‑write data transfer until the host software issues an SD/SDIO STOP or STOP_TRANSMISSION (CMD12) command.†

Data Receive

The data‑receive state machine receives data two clock cycles after the end bit of a data read command, even if the command path detects a response error or response CRC error. If a response is not received from the card because a response timeout occurs, the BIU does not receive a signal that the data transfer is complete. This happens if the command sent by the controller is an illegal operation for the card, which keeps the card from starting a read data transfer.†

If data is not received before the data timeout, the data path signals a data timeout to the BIU and an end to the data transfer done. Based on the value of the transfer_mode bit in the cmd register, the data‑receive state machine gets data from the card data bus in a stream or block(s).†

Figure 72. Data Receive State Machine†
Stream Data Read
A stream‑read data transfer occurs if the transfer_mode bit in the cmd register is set to 1, at which time the data path receives data from the card and writes it to the FIFO buffer. If the FIFO buffer becomes full, the card clock stops and restarts once the FIFO buffer is no longer full.†

An open‑ended stream‑read data transfer occurs if the bytcnt register is set to 0. During this type of data transfer, the data path continuously receives data in a stream until the host software issues an SD/SDIO STOP command. A stream data transfer terminates two clock cycles after the end bit of the STOP command.†

If the bytcnt register contains a nonzero value and the send_auto_stop bit in the cmd register is set to 1, a STOP command is internally generated and loaded into the command path, where the end bit of the STOP command occurs after the last byte of the stream data transfer is received. This data transfer can terminate if the host issues an SD/SDIO STOP or STOP_TRANSMISSION (CMD12) command before all the data bytes are received from the card.†

Single-block Data Read
If the ctype register is set to a 1‑bit, 4‑bit, or 8‑bit data transfer, data is received from 1, 4, or 8 data lines, respectively, and CRC‑16 is separately generated and checked for 1, 4, or 8 data lines, respectively. If there is a CRC‑16 mismatch, the data path signals a data CRC error to the BIU. If the received end bit is not 1, the BIU receives an End-bit Error (EBE).†
Multiple-block Data Read
If the transfer_mode bit in the cmd register is clear and the value of the bytcnt register is not equal to the value of the block_size register, the transfer is a multiple‑block read‑data transfer. The data‑receive state machine receives data in blocks, where the number of bytes in a block is equal to the block size, including the internally‑generated CRC‑16.†

If the ctype register is set to a 1‑bit, 4‑bit, or 8‑bit data transfer, data is received from 1, 4, or 8 data lines, respectively, and CRC‑16 is separately generated and checked for 1, 4, or 8 data lines, respectively. After a data block is received, if the remaining byte count becomes zero, the data path signals a data transfer to the BIU.†

If the remaining data bytes are greater than zero, the data path state machine causes another data block to be received. If CRC‑16 of a received data block does not match the internally‑generated CRC‑16, a data CRC error to the BIU and data reception continue further data transmission until all bytes are transmitted. Additionally, if the end of a received data block is not 1, data on the data path signals terminate the bit error to the CIU and the data‑receive state machine terminates data reception, waits for data timeout, and signals to the BIU that the data transfer is complete.†

If the send_auto_stop bit in the cmd register is set to 1, the SD/SDIO STOP command is internally generated when the last data block is transferred, where no extra bytes are transferred from the card. The end bit of the STOP command might not exactly match the end bit of the last data block.†

If the requested block size for data transfers to cards is less than 4, 16, or 32 bytes for 1‑bit, 4‑bit, or 8‑bit data transfer modes, respectively, the data‑transmit state machine terminates the data transfer when all data is transferred, at which point the internally‑generated STOP command is loaded in the command path. Data received from the card after that are then ignored by the data path.†

If the bytcnt register is 0 (the block size must be greater than zero), the transfer is an open‑ended block transfer. For this type of data transfer, the data‑receive state machine continues the block‑read data transfer until the host software issues an SD/SDIO STOP or STOP_TRANSMISSION (CMD12) command.†

Auto-Stop

The controller internally generates an SD/SDIO STOP command and is loaded in the command path when the send_auto_stop bit in the cmd register is set to 1. The AUTO_STOP command helps to send an exact number of data bytes using a stream read or write for the MMC, and a multiple‑block read or write for SD memory transfer for SD cards. The software must set the send_auto_stop bit according to the following details: †

The following list describes conditions for the AUTO_STOP command:†

  • Stream-read for MMC with byte count greater than zero—The controller generates an internal STOP command and loads it into the command path so that the end bit of the STOP command is sent when the last byte of data is read from the card and no extra data byte is received. If the byte count is less than six (48 bits), a few extra data bytes are received from the card before the end bit of the STOP command is sent.†
  • Stream-write for MMC with byte count greater than zero—The controller generates an internal STOP command and loads it into the command path so that the end bit of the STOP command is sent when the last byte of data is transmitted on the card bus and no extra data byte is transmitted. If the byte count is less than six (48 bits), the data path transmits the data last to meet these condition.†
  • Multiple‑block read memory for SD card with byte count greater than zero—If the block size is less than four (single‑bit data bus), 16 (4‑bit data bus), or 32 (8‑bit data bus), the AUTO_STOP command is loaded in the command path after all the bytes are read. Otherwise, the STOP command is loaded in the command path so that the end bit of the STOP command is sent after the last data block is received.†
  • Multiple‑block write memory for SD card with byte count greater than zero—If the block size is less than three (single‑bit data bus), 12 (4‑bit data bus), or 24 (8‑bit data bus), the AUTO_STOP command is loaded in the command path after all data blocks are transmitted. Otherwise, the STOP command is loaded in the command path so that the end bit of the STOP command is sent after the end bit of the CRC status is received.†
  • Precaution for host software during auto‑stop—When an AUTO_STOP command is issued, the host software must not issue a new command to the controller until the AUTO_STOP command is sent by the controller and the data transfer is complete. If the host issues a new command during a data transfer with the AUTO_STOP command in progress, an AUTO_STOP command might be sent after the new command is sent and its response is received. This can delay sending the STOP command, which transfers extra data bytes. For a stream write, extra data bytes are erroneous data that can corrupt the card data. If the host wants to terminate the data transfer before the data transfer is complete, it can issue an SD/SDIO STOP or STOP_TRANSMISSION (CMD12) command, in which case the controller does not generate an AUTO_STOP command.†
Auto-Stop Generation for MMC Cards
Table 147.  Auto-Stop Generation for MMC Cards†
Transfer Type Byte Count send_auto_stop bit set Comments
Stream read 0 No Open-ended stream
Stream read >0 Yes Auto-stop after all bytes transfer
Stream write 0 No Open-ended stream
Stream write >0 Yes Auto-stop after all bytes transfer
Single-block read >0 No Byte count = 0 is illegal
Single-block write >0 No Byte count = 0 is illegal
Multiple-block read 0 No Open-ended multiple block
Multiple-block read >0 Yes 42 † Pre-defined multiple block
Multiple-block write 0 No Open-ended multiple block
Multiple-block write >0 Yes 42 † Pre-defined multiple block
Auto-Stop Generation for SD Cards
Table 148.  Auto-Stop Generation for SD Cards†
Transfer Type Byte Count send_auto_stop bit set Comments
Single-block read >0 No Byte count = 0 is illegal
Single-block write >0 No Byte count = 0 illegal
Multiple-block read 0 No Open-ended multiple block
Multiple-block read >0 Yes Auto-stop after all bytes transfer
Multiple-block write 0 No Open-ended multiple block
Multiple-block write >0 Yes Auto-stop after all bytes transfer
Auto-Stop Generation for SDIO Cards
Table 149.  Auto-Stop Generation for SDIO Cards†
Transfer Type Byte Count send_auto_stop bit set Comments
Single-block read >0 No Byte count = 0 is illegal
Single-block write >0 No Byte count = 0 illegal
Multiple-block read 0 No Open-ended multiple block
Multiple-block read >0 No Pre-defined multiple block
Multiple-block write 0 No Open-ended multiple block
Multiple-block write >0 No Pre-defined multiple block

Non-Data Transfer Commands that Use Data Path

Some SD/SDIO non‑data transfer commands (commands other than read and write commands) also use the data path.
Table 150.  Non-Data Transfer Commands and Requirements†
  PROGRAM_CSD (CMD27) SEND_WRITE_PROT (CMD30) LOCK_UNLOCK (CMD42) SD_STATUS (ACMD13) SEND_NUM_WR_BLOCKS (ACMD22) SEND_SCR (ACMD51)
Command register programming†

Cmd_index

0x1B=27

0x1E=30

0x2A=42

0x0D=13

0x16=22

0x33=51

Response_expect †

1

1

1

1

1

1

Response_length †

0

0

0

0

0

0

Check_response_crc †

1

1

1

1

1

1

Data_expected †

1

1

1

1

1

1

Read/write †

1

0

1

0

0

0

Transfer_mode †

0

0

0

0

0

0

Send_auto_stop †

0

0

0

0

0

0

Wait_prevdata_complete †

0

0

0

0

0

0

Stop_abort_cmd †

0

0

0

0

0

0

Table 151.  Non-Data Transfer Commands and Requirements (Cont.)†
  PROGRAM_CSD (CMD27) SEND_WRITE_PROT (CMD30) LOCK_UNLOCK (CMD42) SD_STATUS (ACMD13) SEND_NUM_WR_BLOCKS (ACMD22) SEND_SCR (ACMD51)
Command Argument register programming†

Stuff bits

32-bit write protect data address

Stuff bits

Stuff bits

Stuff bits

Stuff bits

Table 152.  Non-Data Transfer Commands and Requirements†
PROGRAM_CSD (CMD27) SEND_WRITE_PROT (CMD30) LOCK_UNLOCK (CMD42) SD_STATUS (ACMD13) SEND_NUM_WR_BLOCKS (ACMD22) SEND_SCR (ACMD51)
Block Size register programing†
16 4 Num_bytes43 64 4 8
Table 153.  Non-Data Transfer Commands and Requirements†
PROGRAM_CSD (CMD27) SEND_WRITE_PROT (CMD30) LOCK_UNLOCK (CMD42) SD_STATUS (ACMD13) SEND_NUM_WR_BLOCKS (ACMD22) SEND_SCR (ACMD51)
Byte Count register programming†
16 4 Num_bytes44 64 4 8

Clock Control Block

The clock control block provides different clock frequencies required for SD/MMC/CE‑ATA cards. The clock control block has one clock divider, which is used to generate different card clock frequencies.†

The clock frequency of a card depends on the following clock ctrl register settings:†

  • clkdiv register—Internal clock dividers are used to generate different clock frequencies required for the cards. The division factor for the clock divider can be set by writing to the clkdiv register. The clock divider is an 8‑bit value that provides a clock division factor from 1 to 510; a value of 0 represents a clock‑divider bypass, a value of 1 represents a divide by 2, a value of 2 represents a divide by 4, and so on.†
  • clksrc register—Set this register to 0 as clock is divided by clock divider 0.†
  • clkena register—The cclk_out card output clock can be enabled or disabled under the following conditions:†
    • cclk_out is enabled when the cclk_enable bit in the clkena register is set to 1 and disabled when set to 0.†
    • Low‑power mode can be enabled by setting the cclk_low_power bit of the clkena register to 1. If low‑power mode is enabled to save card power, the cclk_out signal is disabled when the card is idle for at least eight card clock cycles. Low‑power mode is enabled when a new command is loaded and the command path goes to a non-idle state.†

Under the following conditions, the card clock is stopped or disabled:†

  • Clock can be disabled by writing to the clkena register.†
  • When low‑power mode is selected and the card is idle for at least eight clock cycles.†
  • FIFO buffer is full, data path cannot accept more data from the card, and data transfer is incomplete—to avoid FIFO buffer overflow.†
  • FIFO buffer is empty, data path cannot transmit more data to the card, and data transfer is incomplete—to avoid FIFO buffer underflow.†
Note: The card clock must be disabled through the clkena register before the host software changes the values of the clkdiv and clksrc registers.†

Error Detection

Errors can occur during card operations within the CIU in the following situations.

Response†

  • Response timeout—did not receive the response expected with response start bit within the specified number of clock cycles in the timeout register.†
  • Response CRC error—response is expected and check response CRC requested; response CRC‑7 does not match with the internally‑generated CRC‑7.†
  • Response error—response transmission bit is not 0, command index does not match with the command index of the send command, or response end bit is not 1.†

Data Transmit†

  • No CRC status—during a write data transfer, if the CRC status start bit is not received for two clock cycles after the end bit of the data block is sent out, the data path performs the following actions:†
    • Signals no CRC status error to the BIU†
    • Terminates further data transfer†
    • Signals data transfer done to the BIU†
  • Negative CRC—if the CRC status received after the write data block is negative (that is, not 0b010), the data path signals a data CRC error to the BIU and continues with the data transfer.†
  • Data starvation due to empty FIFO buffer—if the FIFO buffer becomes empty during a write data transmission, or if the card clock stopped and the FIFO buffer remains empty for a data-timeout number of clock cycles, the data path signals a data‑starvation error to the BIU and the data path continues to wait for data in the FIFO buffer.†

Data Receive

  • Data timeout—during a read‑data transfer, if the data start bit is not received before the number of clock cycles specified in the timeout register, the data path does the following action: †
    • Signals a data‑timeout error to the BIU†
    • Terminates further data transfer†
    • Signals data transfer done to BIU†
  • Data SBE—during a 4‑bit or 8‑bit read‑data transfer, if the all‑bit data line does not have a start bit, the data path signals a data SBE to the BIU and waits for a data timeout, after which it signals that the data transfer is done.†
  • Data CRC error—during a read‑data‑block transfer, if the CRC‑16 received does not match with the internally generated CRC‑16, the data path signals a data CRC error to the BIU and continues with the data transfer.†
  • Data EBE—during a read‑data transfer, if the end bit of the received data is not 1, the data path signals an EBE to the BIU, terminates further data transfer, and signals to the BIU that the data transfer is done.†
  • Data starvation due to FIFO buffer full—during a read data transmission and when the FIFO buffer becomes full, the card clock stops. If the FIFO buffer remains full for a data-timeout number of clock cycles, the data path signals a data starvation error to the BIU, by setting the data starvation host timeout bit (hto) in rintsts register to 1, and the data path continues to wait for the FIFO buffer to empty.†

Clocks

Table 154.  SD/MMC Controller Clocks

Clock Name

Direction

Description

l4_mp_clk

In

Clock for SD/MMC controller BIU

sdmmc_clk

In

Clock for SD/MMC controller

sdmmc_cclk_out

Out

Generated output clock for card

sdmmc_clk_divided

Internal

Divide‑by‑four clock of sdmmc_clk

sdmmc_sample_clk

Internal

Phase‑shifted clock of sdmmc_clk_divided used to sample the command and data from the card

sdmmc_drv_clk

Internal

Phase‑shifted clock of sdmmc_clk_divided for controller to drive command and data to the card to meet hold time requirements

Figure 73. SD/MMC Controller Clock Connections - HPSThis figure displays the controller clock connections from the HPS.

The sdmmc_clk clock from the clock manager is divided by four and becomes the sdmmc_clk_divided clock before passing to the phase shifters and the SD/MMC controller CIU. The phase shifters are used to generate the sdmmc_drv_clk and sdmmc_sample_clk clocks. These phase shifters provide up to eight phases shift which include 0, 45, 90, 135, 180, 225, 270, and 315 degrees. The sdmmc_sample_clk clock can be driven by the output from the phase shifter.

Note: The selections of phase shift degree and sdmmc_sample_clk source are done in the system manager. For information about setting the phase shift and selecting the source of the sdmmc_sample_clk clock, refer to the "Clock Setup" section within this document.

The controller generates the sdmmc_cclk_out clock, which is driven to the card. For more information about the generation of the sdmmc_cclk_out clock, refer to the "Clock Control Block" section within this document.

Resets

The SD/MMC controller has one reset signal. The reset manager drives this signal to the SD/MMC controller on a cold or warm reset.

Taking the SD/MMC Controller Out of Reset

When a cold or warm reset is issued in the HPS, the reset manager resets this module and holds it in reset until software releases it.
  • Cold reset—HPS I/O are in frozen state (tri-state with a weak pull-up). Pin Mux and GPIO/LoanIO Mux are in the default state.
  • Warm reset—HPS I/O retain their configuration. The Pin Mux and GPIO/LoanIO Mux do not change during warm reset, meaning it does not reset to the default/reset value and maintain the current settings. Peripheral IP using the HPS I/O performs proper reset of the signals driving the IO.

After the Cortex*-A9 MPCore* CPU boots, it can deassert the reset signal by clearing the appropriate bits in the reset manager's corresponding reset register. For details about reset registers, refer to "Module Reset Signals".

Voltage Switching

This section describes the general steps to switch voltage level.

The SD/MMC cards support various operating voltages, for example 1.8V and 3.0V. If you have a card which is at 1.8V and you eject it and replace it with another card, which is 3.0V, then voltage switching is required.

Many SD cards have an option to signal at 1.8 or 3.0 V, however the initial power-up voltage requirement is 3.0V. To support these different voltage requirements, external transceivers are needed.

The general steps to switch the voltage level requires you to use a SD/MMC voltage-translation transceiver in between the HPS and the SD/MMC card.

Figure 74. Voltage Switching Command Flow Diagram†
(*1) Note: Card returns busy when:†
  • Card executes internal initialization process†
  • Card is High or Extended capacity SD Memory Card and host does not support High†

The following outlines the steps for the voltage switch programming sequence.†

  1. Software Driver starts CMD0, which selects the bus mode as SD.†
  2. After the bus is in SD card mode, CMD8 is started in order to verify if the card is compatible with the SD Memory Card Specification, Version 2.00.†
    CMD8 determines if the card is capable of working within the host supply voltage specified in the VHS (19:16) field of the CMD; the card supports the current host voltage if a response to CMD8 is received.†
  3. ACMD 41 is started.†
    The response to this command informs the software if the card supports voltage switching; bits 38, 36, and 32 are checked by the card argument of ACMD41.†
    Figure 75. ACMD41 Argument
    1. Bit 30 informs the card if host supports SDHC/SDXC or not; this bit should be set to 1'b1.†
    2. Bit 28 can be either 1 or 0.†
    3. Bit 24 should be set to 1'b1, indicating that the host is capable of voltage switching.†
      Figure 76. ACMD41 Response (R3)†
    4. Bit 30 – If set to 1'b1, card supports SDHC/SDXC; if set to 1'b0, card supports only SDSC.†
    5. Bit 24 – If set to 1'b1, card supports voltage switching and is ready for the switch.†
    6. Bit 31 – If set to 1'b1, initialization is over; if set to 1'b0, means initialization in process†

  4. If the card supports voltage switching, then the software must perform the steps discussed for either the “Voltage Switch Normal Scenario” or the “Voltage Switch Error Scenario”, located in the Synopsys® DesignWare Cores Mobile Storage Host Databook.
42 The condition under which the transfer mode is set to block transfer and byte_count is equal to block size is treated as a single-block data transfer command for both MMC and SD cards. If byte_count = n*block_size (n = 2, 3, …), the condition is treated as a predefined multiple-block data transfer command. In the case of an MMC card, the host software can perform a predefined data transfer in two ways: 1) Issue the CMD23 command before issuing CMD18/CMD25 commands to the card – in this case, issue CMD18/CMD25 commands without setting the send_auto_stop bit. 2) Issue CMD18/CMD25 commands without issuing CMD23 command to the card, with the send_auto_stop bit set. In this case, the multiple-block data transfer is terminated by an internally-generated auto-stop command after the programmed byte count.†
43 Num_bytes = Number of bytes specified as per the lock card data structure. Refer to the SD specification and the MMC specification.†
44 Num_bytes = Number of bytes specified as per the lock card data structure. Refer to the SD specification and the MMC specification.†
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