Visible to Intel only — GUID: sfo1410070169298
Ixiasoft
Visible to Intel only — GUID: sfo1410070169298
Ixiasoft
A.4.4.1.1. Default Settings of the SD/MMC Controller
Parameter |
Default |
Register Value |
|
---|---|---|---|
Card type |
1 bit |
The card type register (ctype) in the SD/MMC controller registers (sdmmc) = 0x0 |
|
Bus mode |
— |
SD/MMC62 | |
Timeout |
Maximum |
The timeout register (tmout) = 0xFFFFFFFF |
|
FIFO threshold RX watermark level |
1 |
The RX watermark level field (rx_wmark) of the FIFO threshold watermark register (fifoth) = 0x1 |
|
Clock source |
0 |
The clock source register (clksrc) = 0x0 |
|
Block size |
512 |
The block size register (blksiz) = 0x200 |
|
Clock divider |
Identification mode |
32 |
The clock divider register (clkdiv)= 0x10 (2*16=32) |
Data transfer mode |
Bypass |
The clock divider register (clkdiv)= 0x00 |
|
External Device Power enable | Disabled (Power Off) |
The power_enable bit in the pwren register is programmed to 0x0 out of reset. In Arria 10, the SD/MMC power enable is inverted. To compensate for this active low polarity, you can implement one of three options:
|