Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide

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ID 683704
Date 7/01/2021
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Document Table of Contents
Document Table of Contents x
1. Overview 2. CvP Description 3. CvP Topologies 4. Design Considerations 5. CvP Driver and Registers 6. Understanding the Design Steps for CvP Initialization and Update Mode in Intel® Stratix® 10 7. Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide Archives 8. Document Revision History
1. Overview x
1.1. Benefits of Using CvP 1.2. CvP System 1.3. CvP Modes
1.3. CvP Modes x
1.3.1. CvP Limitations and Restrictions
1.3.1. CvP Limitations and Restrictions x
1.3.1.1. CvP Error Recovery
2. CvP Description x
2.1. Configuration Images 2.2. CvP Modes Compression Features 2.4. Pin Description
2.2. CvP Modes x
2.2.1. CvP Initialization Mode 2.2.2. CvP Update Mode
3. CvP Topologies x
3.1. Single Endpoint 3.2. Multiple Endpoints
4. Design Considerations x
4.1. Designing CvP for an Open System 4.2. Designing CvP for a Closed System
4.1. Designing CvP for an Open System x
4.1.1. FPGA Power Supplies Ramp Time Requirement 4.1.2. PCIe* Wake-Up Time Requirement
4.1.2. PCIe* Wake-Up Time Requirement x
4.1.2.1. For CvP Initialization Mode 4.1.2.2. For CvP Update Mode
5. CvP Driver and Registers x
5.1. CvP Driver Support 5.2. CvP Driver Flow 5.3. VSEC Registers for CvP
5.3. VSEC Registers for CvP x
5.3.1. Vendor Specific Capability Header Register 5.3.2. Vendor Specific Header Register 5.3.3. Intel Marker Register 5.3.4. User Configurable Device/Board ID Register 5.3.5. CvP Status Register 5.3.6. CvP Mode Control Register 5.3.7. CvP Data Registers 5.3.8. CvP Programming Control Register 5.3.9. CvP Credit Register
6. Understanding the Design Steps for CvP Initialization and Update Mode in Intel® Stratix® 10 x
6.1. Implementation of CvP Initialization Mode 6.2. Implementation of CvP Update Mode
6.1. Implementation of CvP Initialization Mode x
6.1.1. Generating the Synthesis HDL files for Avalon® -ST Intel® Stratix® 10 Hard IP for PCI Express 6.1.2. Setting up the CvP Parameters in Device and Pin Options 6.1.3. Compiling the Design 6.1.4. Converting the SOF File 6.1.5. Bringing up the Hardware
6.1.5. Bringing up the Hardware x
6.1.5.1. Installing Open Source CvP Driver in Linux Systems 6.1.5.2. Modifying MSEL/DIP switch on Intel® Stratix® 10 FPGA Development Kit 6.1.5.3. Programming CvP Images
6.2. Implementation of CvP Update Mode x
6.2.1. Instantiating the PCIe* Hard IP 6.2.2. Setting Up the CvP Parameters 6.2.3. Setting up the Base Revision 6.2.4. Setting up and Compile the Updated Revision 6.2.5. Converting the SOF file of the Updated Revision 6.2.6. Programming the FPGA using the Base Revision Image
6.2.3. Setting up the Base Revision x
6.2.3.1. Creating a Reserved Core Partition 6.2.3.2. Defining a Logic Lock Region 6.2.3.3. Compiling and Exporting the Root Partition
1. Overview
2. CvP Description
3. CvP Topologies
4. Design Considerations
5. CvP Driver and Registers
6. Understanding the Design Steps for CvP Initialization and Update Mode in Intel® Stratix® 10
7. Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide Archives
8. Document Revision History

6.2.4. Setting up and Compile the Updated Revision

In this section, you create a new revision that serves as the updated revision of the base design. The new revision reuses the root partition that is exported from the base revision. However, it uses a new core logic.

Perform the following steps to create and compile an updated revision:

  1. To create a new revision, Click Project > Revisions.
  2. The new Revision window appears. To create a new revision, double-click <<new revision>>. The Create Revision dialog box appears.
  3. Specify the revision name in Revision name field.
  4. For the Based on revision, select the base design, In this example design, the base design is called as top.
  5. Enable This project uses a Partition Database (.qdb) file for the root partition. Browse and add the root_partition.qdb generated from the base design. This setting is also present in the Design Partitions window.
  6. For the Revision Type, select same as top.
  7. Click OK and the Intel® Quartus® Prime exist the previous base design and load the new design revision. The new revision opens automatically by Intel® Quartus® Prime. You can confirm the current revision opened by the Intel® Quartus® Prime through the top tool bar.
    Figure 20. Creating Revisions
  8. In the pcie_example_design_update revision, make sure to remove the root_partition.qdb from the Design Partitions Window- Post Final Export File.
    Figure 21. Remove root_partition.qdb
  9. Create the new instance or module that you want to replace/update the partition.
  10. Use entity rebinding assignment in design partitions window to change the logic associated with the reserved core partition. Make sure to select the entity rebinding column when you use the entity rebinding assignment
    Figure 22. Entity Rebinding Column
    For example, First you use green_led as the logic within reserved core partition. Now you change the green_led logic to red_led via entity rebinding, which replaces the green_led instance with a red_led instance.
    Figure 23.  green_led Entity Re-binding to red_led
    Ensure that your Intel® Quartus® Prime project top_update includes source files associated with updated Reserved Core partition logic in Intel® Quartus® Prime.
  11. In the Intel® Quartus® Prime, clickAssignments > Settings > Files and remove the green_led.v file and replace it with red_led.v file.
  12. Verify the following lines in the .qsf file: 
    set_instance_assignment -name ENTITY_REBINDING red_led -to led_inst_0 -entity top_hw
  13. To run compilation, click Processing > Start Compilation.
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