Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide

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ID 683704
Date 7/01/2021
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Document Table of Contents
Document Table of Contents x
1. Overview 2. CvP Description 3. CvP Topologies 4. Design Considerations 5. CvP Driver and Registers 6. Understanding the Design Steps for CvP Initialization and Update Mode in Intel® Stratix® 10 7. Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide Archives 8. Document Revision History
1. Overview x
1.1. Benefits of Using CvP 1.2. CvP System 1.3. CvP Modes
1.3. CvP Modes x
1.3.1. CvP Limitations and Restrictions
1.3.1. CvP Limitations and Restrictions x
1.3.1.1. CvP Error Recovery
2. CvP Description x
2.1. Configuration Images 2.2. CvP Modes Compression Features 2.4. Pin Description
2.2. CvP Modes x
2.2.1. CvP Initialization Mode 2.2.2. CvP Update Mode
3. CvP Topologies x
3.1. Single Endpoint 3.2. Multiple Endpoints
4. Design Considerations x
4.1. Designing CvP for an Open System 4.2. Designing CvP for a Closed System
4.1. Designing CvP for an Open System x
4.1.1. FPGA Power Supplies Ramp Time Requirement 4.1.2. PCIe* Wake-Up Time Requirement
4.1.2. PCIe* Wake-Up Time Requirement x
4.1.2.1. For CvP Initialization Mode 4.1.2.2. For CvP Update Mode
5. CvP Driver and Registers x
5.1. CvP Driver Support 5.2. CvP Driver Flow 5.3. VSEC Registers for CvP
5.3. VSEC Registers for CvP x
5.3.1. Vendor Specific Capability Header Register 5.3.2. Vendor Specific Header Register 5.3.3. Intel Marker Register 5.3.4. User Configurable Device/Board ID Register 5.3.5. CvP Status Register 5.3.6. CvP Mode Control Register 5.3.7. CvP Data Registers 5.3.8. CvP Programming Control Register 5.3.9. CvP Credit Register
6. Understanding the Design Steps for CvP Initialization and Update Mode in Intel® Stratix® 10 x
6.1. Implementation of CvP Initialization Mode 6.2. Implementation of CvP Update Mode
6.1. Implementation of CvP Initialization Mode x
6.1.1. Generating the Synthesis HDL files for Avalon® -ST Intel® Stratix® 10 Hard IP for PCI Express 6.1.2. Setting up the CvP Parameters in Device and Pin Options 6.1.3. Compiling the Design 6.1.4. Converting the SOF File 6.1.5. Bringing up the Hardware
6.1.5. Bringing up the Hardware x
6.1.5.1. Installing Open Source CvP Driver in Linux Systems 6.1.5.2. Modifying MSEL/DIP switch on Intel® Stratix® 10 FPGA Development Kit 6.1.5.3. Programming CvP Images
6.2. Implementation of CvP Update Mode x
6.2.1. Instantiating the PCIe* Hard IP 6.2.2. Setting Up the CvP Parameters 6.2.3. Setting up the Base Revision 6.2.4. Setting up and Compile the Updated Revision 6.2.5. Converting the SOF file of the Updated Revision 6.2.6. Programming the FPGA using the Base Revision Image
6.2.3. Setting up the Base Revision x
6.2.3.1. Creating a Reserved Core Partition 6.2.3.2. Defining a Logic Lock Region 6.2.3.3. Compiling and Exporting the Root Partition
1. Overview
2. CvP Description
3. CvP Topologies
4. Design Considerations
5. CvP Driver and Registers
6. Understanding the Design Steps for CvP Initialization and Update Mode in Intel® Stratix® 10
7. Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide Archives
8. Document Revision History

6.2.6. Programming the FPGA using the Base Revision Image

For CvP update mode, you must program the FPGA using the base revision image through any configuration scheme. After programming completes the FPGA enters user mode.

The following steps illustrate CvP update on the base revision image programmed through JTAG mode.

Before you begin:
  • Connect the Intel® FPGA Download Cable II between your PC USB port and the USB port on the Intel® Stratix® 10 FPGA Development Kit.
  • You must install the altera_cvp driver in your DUT PC system. You can download the open source Linux CvP driver from the CvP Driver.
    Note: The Linux driver provided by Intel® is not a production driver.
  • Set the MSEL switches of the Intel® Stratix® 10 FPGA Development Kit to JTAG mode for CvP update operation.

Follow these steps to program and test CvP update functionality:

  1. Plug the Intel® Stratix® 10 FPGA Development Kit into the PCI Express slot of the DUT PC and power it ON. It is recommended to use the ATX power supply that the development kit includes.
  2. Open the Intel® Quartus® Prime Pro Edition software and click Tools > Programmer.
  3. Click Auto Detect to verify that the Intel® FPGA Download Cable II recognizes the Intel® Stratix® 10 FPGA.
  4. Follow these steps to program the base revision .sof file:
    1. Select Stratix 10 device, and then right click None under File column and select Change File.
    2. Navigate to *.sof file generated from the base revision and click Open.
    3. Under Program/Configure column, select the device. For example, 1SG280LU3S1.
    4. Click Start. The progress bar reaches 100% when device configuration is complete. The device is fully configured and in operation.
    5. After the .sof file is programmed, perform the soft reset on the PC.
    6. Once PC has completed soft rebooting, type the following command in a terminal window to make sure the PCIe link is up and running: lspci -vvv -d1172:.
    7. At this time, the FPGA enters into user mode with a functional PCIe link to the DUT PC and you are ready to use the altera_cvp driver to perform the CvP update.
    8. Follow these steps to program the core.rbf:
    9. Type lspci -vvv -d1172: in a terminal window to make sure that you have an active PCIe link.
    10. Program the core.rbf generated from the updated revision by typing the following command: 
      dd if= <new core.rbf file> of= /dev/altera_cvp bs=4K
      Sample output: 
      <hostname># dd if=top.core.cvpinit.19p3.rbf of=/dev/altera_cvp bs=4K
981+0 records in
981+0 records out
4018176 bytes (4.0 MB) copied, 0.348371 s, 11.5 MB/s
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