Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide

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ID 683704
Date 7/01/2021
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Document Table of Contents
Document Table of Contents x
1. Overview 2. CvP Description 3. CvP Topologies 4. Design Considerations 5. CvP Driver and Registers 6. Understanding the Design Steps for CvP Initialization and Update Mode in Intel® Stratix® 10 7. Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide Archives 8. Document Revision History
1. Overview x
1.1. Benefits of Using CvP 1.2. CvP System 1.3. CvP Modes
1.3. CvP Modes x
1.3.1. CvP Limitations and Restrictions
1.3.1. CvP Limitations and Restrictions x
1.3.1.1. CvP Error Recovery
2. CvP Description x
2.1. Configuration Images 2.2. CvP Modes Compression Features 2.4. Pin Description
2.2. CvP Modes x
2.2.1. CvP Initialization Mode 2.2.2. CvP Update Mode
3. CvP Topologies x
3.1. Single Endpoint 3.2. Multiple Endpoints
4. Design Considerations x
4.1. Designing CvP for an Open System 4.2. Designing CvP for a Closed System
4.1. Designing CvP for an Open System x
4.1.1. FPGA Power Supplies Ramp Time Requirement 4.1.2. PCIe* Wake-Up Time Requirement
4.1.2. PCIe* Wake-Up Time Requirement x
4.1.2.1. For CvP Initialization Mode 4.1.2.2. For CvP Update Mode
5. CvP Driver and Registers x
5.1. CvP Driver Support 5.2. CvP Driver Flow 5.3. VSEC Registers for CvP
5.3. VSEC Registers for CvP x
5.3.1. Vendor Specific Capability Header Register 5.3.2. Vendor Specific Header Register 5.3.3. Intel Marker Register 5.3.4. User Configurable Device/Board ID Register 5.3.5. CvP Status Register 5.3.6. CvP Mode Control Register 5.3.7. CvP Data Registers 5.3.8. CvP Programming Control Register 5.3.9. CvP Credit Register
6. Understanding the Design Steps for CvP Initialization and Update Mode in Intel® Stratix® 10 x
6.1. Implementation of CvP Initialization Mode 6.2. Implementation of CvP Update Mode
6.1. Implementation of CvP Initialization Mode x
6.1.1. Generating the Synthesis HDL files for Avalon® -ST Intel® Stratix® 10 Hard IP for PCI Express 6.1.2. Setting up the CvP Parameters in Device and Pin Options 6.1.3. Compiling the Design 6.1.4. Converting the SOF File 6.1.5. Bringing up the Hardware
6.1.5. Bringing up the Hardware x
6.1.5.1. Installing Open Source CvP Driver in Linux Systems 6.1.5.2. Modifying MSEL/DIP switch on Intel® Stratix® 10 FPGA Development Kit 6.1.5.3. Programming CvP Images
6.2. Implementation of CvP Update Mode x
6.2.1. Instantiating the PCIe* Hard IP 6.2.2. Setting Up the CvP Parameters 6.2.3. Setting up the Base Revision 6.2.4. Setting up and Compile the Updated Revision 6.2.5. Converting the SOF file of the Updated Revision 6.2.6. Programming the FPGA using the Base Revision Image
6.2.3. Setting up the Base Revision x
6.2.3.1. Creating a Reserved Core Partition 6.2.3.2. Defining a Logic Lock Region 6.2.3.3. Compiling and Exporting the Root Partition
1. Overview
2. CvP Description
3. CvP Topologies
4. Design Considerations
5. CvP Driver and Registers
6. Understanding the Design Steps for CvP Initialization and Update Mode in Intel® Stratix® 10
7. Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide Archives
8. Document Revision History

4.1.2.1. For CvP Initialization Mode

To meet the 120 ms wake-up time requirement for the PCIe* Hard IP in CvP initialization mode, you need to use periphery image because the configuration time for periphery image is significantly less than the full FPGA configuration time. You must use the Active Serial x4 (fast mode) configuration scheme for the periphery image configuration.

To ensure successful configuration, all POR-monitored power supplies must ramp up monotonically to the operating range within the 10 ms ramp-up time. The PERST# signal indicates when the FPGA power supplies are within their specified voltage tolerances and the REFCLK is stable1. The embedded hard reset controller triggers after the internal status signal indicates that the periphery image has been loaded. This reset does not trigger off of PERST#. For CvP Initialization mode, the PCIe* link supports the FPGA core image configuration and subsequent PCIe* applications in user mode.

Note: For Gen 2/Gen 3 capable Endpoints, after loading the core bitstream (core.rbf), Intel recommends to verify that the link has been trained to the expected Gen 2/Gen3 rate. If the link is not operating at Gen 2/Gen3, software can trigger the Endpoint to retrain.
Figure 6.  PCIe* Timing Sequence in CvP Initialization Mode
Table 4.  Power-Up Sequence Timing in CvP Initialization Mode
Timing Sequence Timing Range (ms) Description
a 2-6.5 FPGA POR delay time (AS Fast Mode)
b 80 Maximum time from the FPGA power up to the end of periphery configuration in CvP initialization mode (before transceiver calibration)
c 20 Minimum calibration time before PERST# is deasserted
d 60 Minimum transceiver calibration window
e 80 Typical transceiver calibration window
f 100 Minimum PERST# signal active from the host
g 120 Maximum time from the FPGA power up to the end of periphery configuration in CvP initialization mode (include transceiver calibration)
h 20 Maximum PERST# signal inactive time from the host before the PCIe* link enters training state
i 100 Maximum time PCIe* device must enter L0 after PERST# is deasserted
Note: 100 ms timing range is only applicable to PCIe* Gen1/Gen2. PCIe* Gen 3 does not need to meet 100 ms timing requirement.
j 10 Maximum ramp-up time requirement for all POR-monitored power supplies in the FPGA to reach their respective operating range
1 REFCLK must be stable 80 ms after the power supplies are stable in order to achieve the 145 ms link training complete time
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