Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide

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ID 683704
Date 7/01/2021
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Document Table of Contents
Document Table of Contents x
1. Overview 2. CvP Description 3. CvP Topologies 4. Design Considerations 5. CvP Driver and Registers 6. Understanding the Design Steps for CvP Initialization and Update Mode in Intel® Stratix® 10 7. Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide Archives 8. Document Revision History
1. Overview x
1.1. Benefits of Using CvP 1.2. CvP System 1.3. CvP Modes
1.3. CvP Modes x
1.3.1. CvP Limitations and Restrictions
1.3.1. CvP Limitations and Restrictions x
1.3.1.1. CvP Error Recovery
2. CvP Description x
2.1. Configuration Images 2.2. CvP Modes Compression Features 2.4. Pin Description
2.2. CvP Modes x
2.2.1. CvP Initialization Mode 2.2.2. CvP Update Mode
3. CvP Topologies x
3.1. Single Endpoint 3.2. Multiple Endpoints
4. Design Considerations x
4.1. Designing CvP for an Open System 4.2. Designing CvP for a Closed System
4.1. Designing CvP for an Open System x
4.1.1. FPGA Power Supplies Ramp Time Requirement 4.1.2. PCIe* Wake-Up Time Requirement
4.1.2. PCIe* Wake-Up Time Requirement x
4.1.2.1. For CvP Initialization Mode 4.1.2.2. For CvP Update Mode
5. CvP Driver and Registers x
5.1. CvP Driver Support 5.2. CvP Driver Flow 5.3. VSEC Registers for CvP
5.3. VSEC Registers for CvP x
5.3.1. Vendor Specific Capability Header Register 5.3.2. Vendor Specific Header Register 5.3.3. Intel Marker Register 5.3.4. User Configurable Device/Board ID Register 5.3.5. CvP Status Register 5.3.6. CvP Mode Control Register 5.3.7. CvP Data Registers 5.3.8. CvP Programming Control Register 5.3.9. CvP Credit Register
6. Understanding the Design Steps for CvP Initialization and Update Mode in Intel® Stratix® 10 x
6.1. Implementation of CvP Initialization Mode 6.2. Implementation of CvP Update Mode
6.1. Implementation of CvP Initialization Mode x
6.1.1. Generating the Synthesis HDL files for Avalon® -ST Intel® Stratix® 10 Hard IP for PCI Express 6.1.2. Setting up the CvP Parameters in Device and Pin Options 6.1.3. Compiling the Design 6.1.4. Converting the SOF File 6.1.5. Bringing up the Hardware
6.1.5. Bringing up the Hardware x
6.1.5.1. Installing Open Source CvP Driver in Linux Systems 6.1.5.2. Modifying MSEL/DIP switch on Intel® Stratix® 10 FPGA Development Kit 6.1.5.3. Programming CvP Images
6.2. Implementation of CvP Update Mode x
6.2.1. Instantiating the PCIe* Hard IP 6.2.2. Setting Up the CvP Parameters 6.2.3. Setting up the Base Revision 6.2.4. Setting up and Compile the Updated Revision 6.2.5. Converting the SOF file of the Updated Revision 6.2.6. Programming the FPGA using the Base Revision Image
6.2.3. Setting up the Base Revision x
6.2.3.1. Creating a Reserved Core Partition 6.2.3.2. Defining a Logic Lock Region 6.2.3.3. Compiling and Exporting the Root Partition
1. Overview
2. CvP Description
3. CvP Topologies
4. Design Considerations
5. CvP Driver and Registers
6. Understanding the Design Steps for CvP Initialization and Update Mode in Intel® Stratix® 10
7. Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide Archives
8. Document Revision History

2.4. Pin Description

The following table lists the CvP pin descriptions and connection guidelines:
Table 3.  CvP Pin Descriptions and Connection Guidelines
Pin Name Pin Type Pin Description Pin Connection
CvP_CONFDONE Output The CvP_CONFDONE pin is driven low during configuration. When configuration via PCIe* is complete, this signal is actively driven high.

During FPGA configuration in CvP initialization and update mode, you may observe this pin after the CONF_DONE pin goes high to determine if the FPGA is successfully configured.

If this pin is set as dedicated output, the VCCIO_SDM power supply must meet the input voltage specification of the receiving side.

You can assign SDM_IO0, SDM_IO10, SDM_IO11, SDM_IO12, SDM_IO13, SDM_IO14, SDM_IO15 or SDM_IO16 as CvP_CONFDONE in Intel® Quartus® Prime Pro Edition software

INIT_DONE Output The INIT_DONE pin goes high indicating the device has entered user mode upon completion of configuration. Intel recommends using SDM_IO0 pin for implementing the INIT_DONE function, provided that this function is enabled in the Intel® Quartus® Prime Pro Edition software. This pin has a weak pull-down for the correct function during power up.

The INIT_DONE function can also be implemented using other unused SDM I/O pins (with a weak pull-down).

CONF_DONE Output

For normal configuration mode, the CONF_DONE pin drives low before and during configuration. After all configuration data is received without error and the initialization cycle starts, CONF_DONE is driven high.

In CvP initialization mode, CONF_DONE goes high after the periphery is configured.

Intel recommends using SDM_IO16 pin implementing the CONF_DONE function, provided that this function is enabled in the Intel® Quartus® Prime Pro Edition software.

nPERST[L,R][0:2] Input The nPERST pin is only available when you use PCI Express* hard IP.

When the PCIe* hard IP on a side (left or right) is enabled, then nPERST pins on that side cannot be used as general-purpose I/Os (GPIOs). In this case, connect the nPERST pin to the system PCIe* nPERST signal to ensure that both ends of the link start link-training at the same time.

The nPERST pins on a side are available as GPIOs only when the PCIe* hard IP on that side is not enabled.

When this pin is low, the transceivers are in reset. When this pin is high, the transceivers are out of reset.

When you do not use this pin as the fundamental reset, you can use this pin as a user I/O pin

Connect this pin as defined in the Intel® Quartus® Prime Pro Edition software. For more details, refer to Intel® Stratix® 10 Avalon® -MM/ST Interface for PCIe* Solutions User Guide.

This pin is powered by the VCCIO3V supply.

When you connect a 3.0-V supply to VCCIO3V, you must use a diode to clamp the 3.3V LVTTL PCIe* input signal to the VCCIO3V power of the device.

When VCCIO3V is connected to any voltage other than 3.0V, you must use a level translator to shift down the voltage from 3.3V LVTTL to the corresponding voltage level powering the VCCIO3V pin.

Only one nPERST pin is used per PCIe* hard IP. The Intel® Stratix® 10 device components may have all six pins listed even when the specific component might only have 1 or 2 PCIe* hard IPs:
  • nPERSTL0 = Bottom Left PCIe* hard IP & CvP
  • nPERSTL1 = Middle Left PCIe* hard IP (When available)
  • nPERSTL2 Top Left PCIe* hard IP (When available)
  • nPERSTR0 = Bottom Right PCIe* hard IP (When available)
  • nPERSTR1 = Middle Right PCIe* hard IP (When available)
  • nPERSTR2 = Top Right PCIe* hard IP (When available)
Note: For maximum compatibility, always use the bottom left PCIe* Hard IP first, as this is the only location that supports Configuration via Protocol (CvP) using the PCIe* link.
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