Read signal for the parameter specified in param[] input port and fed to data_out[] output port.

Signal indicating the parameter specified on the param[] port should be read. The number of bits set on data_out[] depends on the parameter type. The signal is sampled at the rising clock edge. Assert the signal for only one clock cycle to prevent the parameter from being read again in a subsequent clock cycle.

The busy signal is activated as soon as read_param is read as active. While the parameter is being read, the busy signal remains asserted, and data_out[] has invalid data. When the busy signal is deactivated, data_out[] is valid, another parameter can be read.

Write signal for parameter specified in param[] and with value specified in data_in[].

Signal indicating parameter specified with param[] should be written into remote update block with the value specified in data_in[]. The number of bits read from data_in[] depends on the parameter type.

The signal is sampled at the rising clock edge. The signal should be asserted for only one clock cycle to prevent the parameter from being rewritten on a subsequent clock cycle. The busy signal is activated as soon as write_param is read as being active. While the parameter is being written, the busy signal remains asserted, and input to data_in[] is ignored. When the busy signal is deactivated, another parameter can be written. This signal is only valid in factory configuration mode because parameters cannot be written in application configuration mode.

Bus that specifies which parameter need to be read or updated.

A 3-bit bus that selects the parameter to be read or updated. If left unconnected, the default value for this port is 000.

For more information, refer to Parameters.

Data input for writing parameter data into the remote update block. Input bus for parameter data.

For some parameters, not all bits are used. In this case, the lower-order bits are used (for example, status values use bits [4:0]).

If left unconnected, this bus defaults to 0. The port is ignored if the current configuration is the Application configuration.

A 24-bit bus width in the Intel® Quartus® Prime software version 13.0 or earlier. For the Intel® Quartus® Prime software version 13.1 and later, the bus widths are as follow:

• 24-bit bus width—using 3-byte addressing configuration device, for example EPCS128.
• 32-bit bus width—using 4-byte addressing configuration device, for example EPCQ256.

Signal indicating that reconfiguration of the part should begin using the current parameter settings. A value of 1 indicates reconfiguration should begin. This signal is ignored while the busy signal is asserted to ensure all parameters are completely written before reconfiguration begins.

reset_timer

Reset signal for watchdog timer.

Signal indicating the internal watchdog timer should be reset. Unlike other inputs, this signal is not affected by the busy signal and can reset the timer even when the busy signal is asserted.

A falling edge of this signal triggers a reset of the user watchdog timer.

For the timing specification of this parameter, refer to the specific device handbook.

Clock input to the remote update block.

Clock input to control the machine and to drive the remote update block during the update of parameters.

This port must be connected to a valid clock.

This is an active high signal. Asserting this signal high will reset the IP core.

Asynchronous reset input to the IP core to initialize the machine to a valid state. The machine must be reset before first use, otherwise the state is not guaranteed to be valid.

Busy signal that indicates when remote update block is reading or writing data.

While this signal is asserted, the machine ignores most of its inputs and cannot be altered until the machine deasserts this signal. Therefore, changes are made only when the machine is not busy.

This signal goes high when read_param or write_param is asserted, and remains high until the read or write operation completes.

Data output when reading parameters.

This bus holds read parameter data from the remote update block. The param[] value specifies the parameter to read. When the read_param signal is asserted, the parameter value is loaded and driven on this bus. Data is valid when the busy signal is deasserted.

If left unconnected, the default value for the port is 0. The width of this bus is device-dependent:

For the Intel® Quartus® Prime software version 13.0 or earlier, the bus widths is 24 bits. For the Intel® Quartus® Prime software version 13.1 and later are as follow:

• 24-bit bus width—using 3-byte addressing configuration device, for example EPCS128.
• 32-bit bus width—using 4-byte addressing configuration device, for example EPCQ256.

Input from the altasmi_parallel component.

Available when the check_app_pof parameter is set to true.

A logic high on this pin indicates that the ASMI Parallel Intel® FPGA IP core is busy processing the operation. The Remote Update Intel® FPGA IP core waits for this pin to go low before initiating another operation.

Wire this pin to the asmi_busy output port of the ASMI Parallel Intel® FPGA IP core.

Input from the altasmi_parallel component.

Available when the check_app_pof parameter is set to true.

A logic high on this pin indicates valid data in the asmi_dataout[7..0] output port of the ASMI Parallel Intel® FPGA IP core.

Wire this pin to the asmi_data_valid output port of the ASMI Parallel Intel® FPGA IP core.

Input from the altasmi_parallel component.

Available when the check_app_pof parameter is set to true.

The Remote Update Intel® FPGA IP core presents the address information on this pin before initiating the read operation on the ASMI Parallel Intel® FPGA IP core.

Detects an invalid application configuration image.

Available when the check_app_pof parameter is set to TRUE.

A logic high on this pin indicates that the Remote Update Intel® FPGA IP core detects an invalid application configuration image. If asserted high, you must take corrective action by reloading a new application configuration image or specifying a different address location in the EPCS or EPCQ that contains a valid application configuration image. Wire this pin based on your system requirement.

Address signal to the altasmi_parallel component.

Available when the check_app_pof parameter is set to TRUE. The Remote Update Intel® FPGA IP core presents the address information on this pin before initiating the read operation on the ASMI Parallel Intel® FPGA IP core.

Read signal to the altasmi_parallel component.

Available when the check_app_pof parameter is set to TRUE. A logic high on this pin initiates the read operation on the ASMI Parallel Intel® FPGA IP core.

Wire this pin to the asmi_read input port of the ASMI Parallel Intel® FPGA IP core.

Read enable signal to the altasmi_parallel component.

Available when the check_app_pof parameter is set to TRUE. This pin enables the read operation on the ASMI Parallel Intel® FPGA IP core.

Wire this pin to the asmi_rden input port of the ASMI Parallel Intel® FPGA IP core.